{"product_id":"asic-and-fpga-verification-a-guide-to-component-modeling-1","title":"ASIC and FPGA Verification: A Guide to Component Modeling","description":"Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL\/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs. \u003cbr\u003e\u003cbr\u003eASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.\u003cbr\u003e\u003cbr\u003e*Provides numerous models and a clearly defined methodology for performing board-level simulation.\u003cbr\u003e*Covers the details of modeling for verification of both logic and timing.  \u003cbr\u003e*First book to collect and teach techniques for using VHDL to model \"off-the-shelf\" or \"IP\" digital components for use in FPGA and board-level design verification.","brand":"Elsevier S \u0026 T","offers":[{"title":"perpetual","offer_id":44507846967393,"sku":"9780125105811","price":26.25,"currency_code":"KWD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0268\/9869\/4241\/files\/480_d81fc88b-31c5-4d48-b648-81189a130995.jpg?v=1778629770","url":"https:\/\/ebooks.aafaqeducation.com\/products\/asic-and-fpga-verification-a-guide-to-component-modeling-1","provider":"ebook.aafaqeducation","version":"1.0","type":"link"}