Elsevier S & T

ARM System Developer's Guide: Designing and Optimizing System Software

Sloss, Andrew; Symes, Dominic; Wright, Chris

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Table of contents
  • Cover
  • Copyright Pageiv
  • Contentsv
  • About the Authorsii
  • Prefacexi
  • Chapter 1. ARM Embedded Systems3
  • 1.1 The RISC design philosophy4
  • 1.2 The ARM Design Philosophy5
  • 1.3 Embedded System Hardware6
  • 1.4 Embedded System Software12
  • 1.5 Summary15
  • Chapter 2. ARM Processor Fundamentals19
  • 2.1 Registers21
  • 2.2 Current Program Status Register22
  • 2.3 Pipeline29
  • 2.4 Exceptions, Interrupts, and the Vector Table33
  • 2.5 Core Extensions34
  • 2.6 Architecture Revisions37
  • 2.7 ARM Processor Families38
  • 2.8 Summary43
  • Chapter 3. Introduction to the ARM Instruction Set47
  • 3.1 Data Processing Instructions50
  • 3.2 Branch Instructions58
  • 3.3 Load-Store Instructions60
  • 3.4 Software Interrupt Instruction73
  • 3.5 Program Status Register Instructions75
  • 3.6 Loading Constants78
  • 3.7 ARMv5E Extensions79
  • 3.8 Conditional Execution82
  • 3.9 Summary84
  • Chapter 4. Introduction to the Thumb Instruction Set87
  • 4.1 Thumb Register Usage89
  • 4.2 ARM-Thumb Interworking90
  • 4.3 Other Branch Instructions92
  • 4.4 Data Processing Instructions93
  • 4.5 Single-Register Load-Store Instructions96
  • 4.6 Multiple-Register Load-Store Instructions97
  • 4.7 Stack Instructions98
  • 4.8 Software Interrupt Instruction99
  • 4.9 Summary100
  • Chapter 5. Efficient C Programming103
  • 5.1 Overview of C Compilers and Optimization104
  • 5.2 Basic C Data Types105
  • 5.3 C Looping Structures113
  • 5.4 Register Allocation120
  • 5.5 Function Calls122
  • 5.6 Pointer Aliasing127
  • 5.7 Structure Arrangement130
  • 5.8 Bit-fields133
  • 5.9 Unaligned Data and Endianness136
  • 5.10 Division140
  • 5.11 Floating Point149
  • 5.12 Inline Functions and Inline Assembly149
  • 5.13 Portability Issues153
  • 5.14 Summary155
  • Chapter 6. Writing and Optimizing ARM Assembly Code157
  • 6.1 Writing Assembly Code158
  • 6.2 Profiling and Cycle Counting163
  • 6.3 Instruction Scheduling163
  • 6.4 Register Allocation171
  • 6.5 Conditional Execution180
  • 6.6 Looping Constructs183
  • 6.7 Bit Manipulation191
  • 6.8 Efficient Switches197
  • 6.9 Handling Unaligned Data201
  • 6.10 Summary204
  • Chapter 7. Optimized Primitives207
  • 7.1 Double-Precision Integer Multiplication208
  • 7.2 Integer Normalization and Count Leading Zeros212
  • 7.3 Division216
  • 7.4 Square Roots238
  • 7.5 Transcendental Functions: log, exp, sin, cos241
  • 7.6 Endian Reversal and Bit Operations248
  • 7.7 Saturated and Rounded Arithmetic253
  • 7.8 Random Number Generation255
  • 7.9 Summary256
  • Chapter 8. Digital Signal Processing259
  • 8.1 Representing a Digital Signal260
  • 8.2 Introduction to DSP on the ARM269
  • 8.3 FIR filters280
  • 8.4 IIR Filters294
  • 8.5 The Discrete Fourier Transform303
  • 8.6 Summary314
  • Chapter 9. Exception and Interrupt Handling317
  • 9.1 Exception Handling318
  • 9.2 Interrupts324
  • 9.3 Interrupt Handling Schemes333
  • 9.4 Summary364
  • Chapter 10. Firmware367
  • 10.1 Firmware and Bootloader367
  • 10.2 Example: Sandstone372
  • 10.3 Summary379
  • Chapter 11. Embedded Operating Systems381
  • 11.1 Fundamental Components381
  • 11.2 Example: Simple Little Operating System383
  • 11.3 Summary400
  • Chapter 12. Caches403
  • 12.1 The Memory Hierarchy and Cache Memory404
  • 12.2 Cache Architecture408
  • 12.3 Cache Policy418
  • 12.4 Coprocessor 15 and Caches423
  • 12.5 Flushing and Cleaning Cache Memory423
  • 12.6 Cache Lockdown443
  • 12.7 Caches and Software Performance456
  • 12.8 Summary457
  • Chapter 13. Memory Protection Units461
  • 13.1 Protected Regions463
  • 13.2 Initializing the MPU, Caches, and Write Buffer465
  • 13.3 Demonstration of an MPU system478
  • 13.4 Summary487
  • Chapter 14. Memory Management Units491
  • 14.1 Moving from an MPU to an MMU492
  • 14.2 How Virtual Memory Works493
  • 14.3 Details of the ARM MMU501
  • 14.4 Page Tables501
  • 14.5 The Translation Lookaside Buffer506
  • 14.6 Domains and Memory Access Permission510
  • 14.7 The Caches and Write Buffer512
  • 14.8 Coprocessor 15 and MMU Configuration513
  • 14.9 The Fast Context Switch Extension515
  • 14.10 Demonstration: A Small Virtual Memory System520
  • 14.11 The Demonstration as mmuSLOS545
  • 14.12 Summary545
  • Chapter 15. The Future of the Architecture549
  • 15.1 Advanced DSP and SIMD Support in ARMv6550
  • 15.2 System and Multiprocessor Support Additions to ARMv6560
  • 15.3 ARMv6 Implementations563
  • 15.4 Future Technologies beyond ARMv6563
  • 15.5 Summary566
  • Appendix A. ARM and Thumb Assembler Instructions569
  • A.1 Using This Appendix569
  • A.2 Syntax570
  • A.3 Alphabetical List of ARM and Thumb Instructions573
  • A.4 ARM Assembler Quick Reference620
  • A.5 GNU Assembler Quick Reference631
  • Appendix B. ARM and Thumb Instruction Encodings637
  • B.1 ARM Instruction Set Encodings637
  • B.2 Thumb Instruction Set Encodings638
  • B.3 Program Status Registers645
  • Appendix C. Processors and Architecture647
  • C.1 ARM Naming Convention647
  • C.2 Core and Architectures647
  • Appendix D. Instruction Cycle Timings651
  • D.1 Using the Instruction Cycle Timing Tables651
  • D.2 ARM7TDMI Instruction Cycle Timings653
  • D.3 ARM9TDMI Instruction Cycle Timings654
  • D.4 StrongARM1 Instruction Cycle Timings655
  • D.5 ARM9E Instruction Cycle Timings656
  • D.6 ARM10E Instruction Cycle Timings658
  • D.7 Intel XScale Instruction Cycle Timings659
  • D.8 ARM11 Cycle Timings661
  • Appendix E. Suggested Reading667
  • E.1 ARM References667
  • E.2 Algorithm References667
  • E.3 Memory Management and Cache Architecture (Hardware Overview and Reference)668
  • E.4 Operating System References668
  • Index669
Book details
  • Vendor Elsevier S & T
  • SKU 9781558608740
  • ISBN-13 9780080490496
  • Author Sloss, Andrew; Symes, Dominic; Wright, Chris
  • Category Computers
  • Subject General

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Over the last ten years, the ARM architecture has become one of the most pervasive architectures in the world, with more than 2 billion ARM-based processors embedded in products ranging from cell phones to automotive braking systems. A world-wide community of ARM developers in semiconductor and product design companies includes software developers, system designers and hardware engineers. To date no book has directly addressed their need to develop the system and software for an ARM-based system. This text fills that gap.

This book provides a comprehensive description of the operation of the ARM core from a developer’s perspective with a clear emphasis on software. It demonstrates not only how to write efficient ARM software in C and assembly but also how to optimize code. Example code throughout the book can be integrated into commercial products or used as templates to enable quick creation of productive software.

The book covers both the ARM and Thumb instruction sets, covers Intel's XScale Processors, outlines distinctions among the versions of the ARM architecture, demonstrates how to implement DSP algorithms, explains exception and interrupt handling, describes the cache technologies that surround the ARM cores as well as the most efficient memory management techniques. A final chapter looks forward to the future of the ARM architecture considering ARMv6, the latest change to the instruction set, which has been designed to improve the DSP and media processing capabilities of the architecture.

* No other book describes the ARM core from a system and software perspective.
* Author team combines extensive ARM software engineering experience with an in-depth knowledge of ARM developer needs.
* Practical, executable code is fully explained in the book and available on the publisher's Website.
* Includes a simple embedded operating system.