Elsevier S & T

ASIC and FPGA Verification: A Guide to Component Modeling

Munden, Richard

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Table of contents

Cover
ABOUT THE AUTHORii
Table of Contentsvii
PREFACExv
Historical Backgroundxv
Verilog, VHDL, and the Origin of VITALxvi
The VITAL Specificationxvi
The Free Model Foundryxvii
Structure of the Bookxviii
Intended Audiencexix
Resources for Help and Informationxix
Acknowledgmentsxx
PART I INTRODUCTION1
CHAPTER 1 INTRODUCTION TO BOARD-LEVEL VERIFICATION3
1.1 Why Models Are Needed3
1.1.1 Prototyping3
1.1.2 Simulation4
1.2 Definition of a Model5
1.2.1 Levels of Abstraction6
1.2.2 Model Types7
1.2.3 Technology-Independent Models9
1.3 Design Methods and Models10
1.4 How Models Fit in the FPGA/ASIC Design Flow10
1.4.1 The Design/Verification Flow11
1.5 Where to Get Models13
1.6 Summary14
CHAPTER 2 TOUR OF A SIMPLE MODEL15
2.1 Formatting15
2.2 Standard Interfaces17
2.3 Model Delays18
2.4 VITAL Additions19
2.4.1 VITAL Delay Types19
2.4.2 VITAL Attributes20
2.4.3 VITAL Primitive Call21
2.4.4 VITAL Processes22
2.4.5 VitalPathDelays24
2.5 Interconnect Delays25
2.6 Finishing Touches27
2.7 Summary31
PART II RESOURCES AND STANDARDS33
CHAPTER 3 VHDL PACKAGES FOR COMPONENT MODELS35
3.1 STD_LOGIC_116435
3.1.1 Type Declarations36
3.1.2 Functions37
3.2 VITAL_Timing37
3.2.1 Declarations37
3.2.2 Procedures38
3.3 VITAL_Primitives39
3.3.1 Declarations40
3.3.2 Functions and Procedures40
3.4 VITAL_Memory41
3.4.1 Memory Functionality41
3.4.2 Memory Timing Specification42
3.4.3 Memory Timing Checks42
3.5 FMF Packages42
3.5.1 FMF gen_utils and ecl_utils43
3.5.2 FMF ff_package44
3.5.3 FMF Conversions45
3.6 Summary45
CHAPTER 4 AN INTRODUCTION TO SDF47
4.1 Overview of an SDF File47
4.1.1 Header48
4.1.2 Cell50
4.1.3 Timing Specifications50
4.2 SDF Capabilities52
4.2.1 Circuit Delays52
4.2.2 Timing Checks55
4.3 Summary58
CHAPTER 5 ANATOMY OF A VITAL MODEL59
5.1 Level 0 Guidelines59
5.1.1 Backannotation60
5.1.2 Timing Generics60
5.1.3 VitalDelayTypes61
5.2 Level 1 Guidelines63
5.2.1 Wire Delay Block63
5.2.2 Negative Constraint Block65
5.2.3 Processes66
5.2.4 VITAL Primitives70
5.2.5 Concurrent Procedure Section70
5.3 Summary70
CHAPTER 6 MODELING DELAYS73
6.1 Delay Types and Glitches73
6.1.1 Transport and Inertial Delays73
6.1.2 Glitches74
6.2 Distributed Delays75
6.3 Pin-to-Pin Delays75
6.4 Path Delay Procedures76
6.5 Using VPDs82
6.6 Generates and VPDs83
6.7 Device Delays83
6.8 Backannotating Path Delays88
6.9 Interconnect Delays89
6.10 Summary90
CHAPTER 7 VITAL TABLES91
7.1 Advantages of Truth and State Tables91
7.2 Truth Tables92
7.2.1 Truth Table Construction92
7.2.2 VITAL Table Symbols92
7.2.3 Truth Table Usage93
7.3 State Tables97
7.3.1 State Table Symbols97
7.3.2 State Table Construction97
7.3.3 State Table Usage98
7.3.4 State Table Algorithm99
7.4 Reducing Pessimism100
7.5 Memory Tables101
7.5.1 Memory Table Symbols101
7.5.2 Memory Table Construction102
7.5.3 Memory Table Usage103
7.6 Summary106
CHAPTER 8 TIMING CONSTRAINTS107
8.1 The Purpose of Timing Constraint Checks107
8.2 Using Timing Constraint Checks in VITAL Models108
8.2.1 Setup/Hold Checks108
8.2.2 Period/Pulsewidth Checks112
8.2.3 Recovery/Removal Checks114
8.2.4 Skew Checks117
8.3 Violations121
8.4 Summary122
PART III MODELING BASICS123
CHAPTER 9 MODELING COMPONENTS WITH REGISTERS125
9.1 Anatomy of a Flip-Flop125
9.1.1 The Entity125
9.1.2 The Architecture129
9.1.3 A VITAL Process131
9.1.4 Functionality Section133
9.1.5 Path Delay134
9.1.6 The BŽ Side135
9.2 Anatomy of a Latch137
9.2.1 The Entity138
9.2.2 The Architecture140
9.3 Summary146
CHAPTER 10 CONDITIONAL DELAYS AND TIMING CONSTRAINTS147
10.1 Conditional Delays in VITAL147
10.2 Conditional Delays in SDF149
10.3 Conditional Delay Alternatives150
10.4 Mapping SDF to VITAL152
10.5 Conditional Timing Checks in VITAL153
10.6 Summary156
CHAPTER 11 NEGATIVE TIMING CONSTRAINTS157
11.1 How Negative Constraints Work157
11.2 Modeling Negative Constraints158
11.3 How Simulators Handle Negative Constraints176
11.4 Ramifications177
11.5 Summary178
CHAPTER 12 TIMING FILES AND BACKANNOTATION179
12.1 Anatomy of a Timing File179
12.1.1 Header179
12.1.2 Body181
12.1.3 FMFTIME181
12.2 Separate Timing Specifications182
12.3 Importing Timing Values183
12.4 Custom Timing Sections183
12.5 Generating Timing Files184
12.6 Generating SDF Files184
12.7 Backannotation and Hierarchy185
12.8 Summary187
PART IV ADVANCED MODELING189
CHAPTER 13 ADDING TIMING TO YOUR RTL CODE191
13.1 Using VITAL to Simulate Your RTL191
13.2 The Basic Wrapper192
13.3 A Wrapper for Verilog RTL206
13.4 Modeling Delays in Designs with Internal Clocks206
13.5 Caveats207
13.6 Summary208
CHAPTER 14 MODELING MEMORIES209
14.1 Memory Arrays209
14.1.1 The Shelor Method210
14.1.2 The VITAL_Memory Package211
14.2 Modeling Memory Functionality211
14.2.1 Using the Behavioral (Shelor) Method211
14.2.2 Using the VITAL2000 Method223
14.3 VITAL_Memory Path Delays231
14.4 VITAL_Memory Timing Constraints232
14.5 Preloading Memories235
14.5.1 Behavioral Memory Preload235
14.5.2 VITAL_Memory Preload237
14.6 Modeling Other Memory Types238
14.6.1 Synchronous Static RAM238
14.6.2 DRAM241
14.6.3 SDRAM244
14.7 Summary249
CHAPTER 15 CONSIDERATIONS FOR COMPONENT MODELING251
15.1 Component Models and Netlisters251
15.2 File Contents253
15.3 Generics Passed from the Schematic253
15.3.1 Timing Generics253
15.3.2 Control Generics253
15.4 Integrating Models into a Schematic Capture System254
15.4.1 Library Structure254
15.4.2 Technology Independence255
15.4.3 Directories255
15.4.4 Map Files256
15.5 Using Models in the Design Process256
15.5.1 VHDL Libraries257
15.5.2 Schematic Entry257
15.5.3 Netlisting the Design258
15.5.4 VHDL Compilation259
15.5.5 SDF Generation259
15.5.6 Simulation261
15.5.7 Layout261
15.5.8 Signal Analysis262
15.5.9 Timing Backannotation262
15.5.10 Timing Analysis262
15.6 Special Considerations262
15.6.1 Schematic Considerations262
15.6.2 Model Considerations263
15.7 Summary266
CHAPTER 16 MODELING COMPONENT-CENTRIC FEATURES269
16.1 Differential Inputs269
16.2 Bus Hold279
16.3 PLLs and DLLs282
16.4 Assertions284
16.5 Modifying Behavior with the TimingModel Generic285
16.6 State Machines285
16.7 Mixed Signal Devices288
16.8 Summary294
CHAPTER 17 TESTBENCHES FOR COMPONENT MODELS295
17.1 About Testbenches295
17.1.1 Tools295
17.2 Testbench Styles296
17.2.1 The Empty Testbench296
17.2.2 The Linear Testbench296
17.2.3 The Transactor Testbench296
17.3 Using Assertions297
17.4 Using Transactors298
17.5 Testing Memory Models301
17.6 Summary308
Index309

Book details

Vendor Elsevier S & T
SKU 9780125105811
ISBN-13 9780080475929
Author Munden, Richard
Category Technology & Engineering
Subject Digital

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Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs.

ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.

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