Comprehensive Functional Verification: The Complete Industry Cycle
Regular price
32.000 KD
inc. VAT
Couldn't load pickup availability
Table of contents
- Cover
- Author Biosiv
- FOREWORDix
- Table of contentsxiii
- PREFACExxi
- THE VERIFICATION CYCLExxii
- STRUCTURE OF THE BOOKxxii
- BASIC KNOWLEDGE NEEDED FOR THIS BOOKxxiii
- EXERCISES AND SUPPORTING MATERIALSxxiii
- ACKNOWLEDGEMENTSxxv
- PART I: INTRODUCTION TO VERIFICATION3
- CHAPTER 1: VERIFICATION IN THE CHIP DESIGN PROCESS5
- 1.1 INTRODUCTION TO FUNCTIONAL VERIFICATION5
- 1.2 THE VERIFICATION CHALLENGE8
- 1.2.1 The Challenge of State Space Explosion9
- 1.2.2 The Challenge of Detecting Incorrect Behavior12
- 1.3 MISSION AND GOALS OF VERIFICATION14
- 1.3.1 Verification Engineer MustsŽ18
- 1.4 COST OF VERIFICATION20
- 1.4.1 Engineering Costs and the Need for an Independent Verification Team20
- 1.4.2 DA Tools21
- 1.4.3 Time22
- 1.5 AREAS OF VERIFICATION BEYOND THE SCOPE OF THIS BOOK23
- 1.6 THE VERIFICATION CYCLE: A STRUCTURED PROCESS24
- 1.6.1 Functional Specification25
- 1.6.2 Create Verification Plan26
- 1.6.3 Develop Environment27
- 1.6.4 Debug HDL and Environment27
- 1.6.5 Regression28
- 1.6.6 Fabricate Hardware28
- 1.6.7 Debug Fabricated Hardware (Systems Test)29
- 1.6.8 Escape Analysis29
- 1.6.9 Common Verification Cycle Breakdowns30
- 1.7 SUMMARY31
- 1.8 EXERCISES32
- CHAPTER 2: VERIFICATION FLOW35
- 2.1 VERIFICATION HIERARCHY35
- 2.1.1 Levels of Verification36
- 2.1.2 What Level To Choose?41
- 2.2 STRATEGY OF VERIFICATION45
- 2.2.1 Driving Principles45
- 2.2.2 Checking Strategies50
- 2.2.3 Checking the Black Box55
- 2.2.4 Putting It All Together59
- 2.2.5 The General Simulation Environment61
- 2.2.6 Verification Methodology Evolution62
- 2.3 SUMMARY68
- 2.4 EXERCISES69
- CHAPTER 3: FUNDAMENTALS OF SIMULATION-BASED VERIFICATION73
- 3.1 BASIC VERIFICATION ENVIRONMENT: A TEST BENCH73
- 3.1.1 Stimulus Component74
- 3.1.2 Monitor80
- 3.1.3 Checker82
- 3.1.4 Scoreboard83
- 3.1.5 Design Under Verification85
- 3.2 OBSERVATION POINTS: BLACK-BOX, WHITE-BOX, AND GREY-BOX VERIFICATION86
- 3.2.1 Black Box86
- 3.2.2 White Box87
- 3.2.3 Grey Box88
- 3.3 ASSERTION-BASED VERIFICATION: AN OVERVIEW89
- 3.3.1 The Importance of Assertions90
- 3.3.2 Assertions Express Design Intent92
- 3.3.3 Classification of Assertions94
- 3.4 TEST BENCHES AND TESTING STRATEGIES95
- 3.4.1 Deterministic Test Benches95
- 3.4.2 Self-Checking Test Benches97
- 3.5 SUMMARY101
- 3.6 EXERCISES102
- CHAPTER 4: THE VERIFICATION PLAN103
- 4.1 THE FUNCTIONAL SPECIFICATION103
- 4.2 THE EVOLUTION OF THE VERIFICATION PLAN104
- 4.3 CONTENTS OF THE VERIFICATION PLAN106
- 4.3.1 Description of Verification Levels106
- 4.3.2 Required Tools107
- 4.3.3 Risks and Dependencies108
- 4.3.4 Functions to be Verified109
- 4.3.5 Specific Tests and Methods: Environment111
- 4.3.6 Coverage Requirements115
- 4.3.7 Test Case Scenarios: Matrix116
- 4.3.8 Resource Requirements117
- 4.3.9 Schedule Details118
- 4.4 VERIFICATION EXAMPLE: CALC1121
- 4.4.1 Design Description121
- 4.4.2 Creating the Verification Plan for Calc1125
- 4.4.3 Deterministic Verification of Calc1131
- 4.5 SUMMARY136
- 4.6 EXERCISES136
- PART II: SIMULATION-BASED VERIFICATION139
- CHAPTER 5: HARDWARE DESCRIPTION LANGUAGES AND SIMULATION ENGINES141
- 5.1 HARDWARE DESCRIPTION LANGUAGES143
- 5.1.1 HDL Modeling Levels143
- 5.1.2 Verification Aspects of HDLs153
- 5.2 SIMULATION ENGINES: INTRODUCTION159
- 5.2.1 Speed Versus Accuracy160
- 5.2.2 Making the Right Methodology Choices162
- 5.3 EVENT-DRIVEN SIMULATION162
- 5.3.1 Hierarchical Model Network163
- 5.3.2 Model Evaluation Over Time165
- 5.3.3 Event-Driven Control of Model Evaluation167
- 5.3.4 Implementation Sketch of an Event-Driven Simulation Engine172
- 5.4 IMPROVING SIMULATION THROUGHPUT178
- 5.5 CYCLE-BASED SIMULATION182
- 5.5.1 Synchronous Design183
- 5.5.2 The Cycle-Based Simulation Algorithm184
- 5.5.3 Extensions to Basic Cycle-Based Simulation Engines188
- 5.6 WAVEFORM VIEWERS191
- 5.7 SUMMARY195
- 5.8 EXERCISES197
- CHAPTER 6: CREATING ENVIRONMENTS199
- 6.1 TEST BENCH WRITING TOOLS200
- 6.1.1 HDL Languages as Test Bench Tool201
- 6.1.2 C/C++ Libraries207
- 6.1.3 High-Level Verification Languages230
- 6.1.4 Other Test Bench Tools241
- 6.2 VERIFICATION COVERAGE243
- 6.2.1 Overview244
- 6.2.2 Functional Verification Test Coverage Versus Manufacturing Test Coverage246
- 6.2.3 Structural Coverage247
- 6.2.4 Functional Coverage251
- 6.2.5 Coverage Bulk Data Collection and Management254
- 6.2.6 The Right Coverage Analysis Strategy255
- 6.3 SUMMARY256
- 6.4 EXERCISES258
- CHAPTER 7: STRATEGIES FOR SIMULATION-BASED STIMULUS GENERATION259
- 7.1 CALC2 OVERVIEW260
- 7.1.1 Calc2 Verification Plan263
- 7.1.2 Calc2 and the Strategies for Stimulus Generation269
- 7.2 STRATEGIES FOR STIMULUS GENERATION270
- 7.2.1 Types of Stimulus Generation270
- 7.2.2 General Algorithms for Stimulus Components275
- 7.2.3 Applying the Four Types of Stimulus Generation to Calc2277
- 7.2.4 Seeding Random Test Cases294
- 7.2.5 Constraint Solving in Random Environments297
- 7.2.6 Coverage Techniques in Random Environments301
- 7.2.7 Making Rare Events Occur303
- 7.2.8 Stimulus Generation of Deadlocks and Livelocks306
- 7.3 SUMMARY310
- 7.4 EXERCISES311
- CHAPTER 8: STRATEGIES FOR RESULTS CHECKING IN SIMULATION-BASED VERIFICATION313
- 8.1 TYPES OF RESULT CHECKING313
- 8.1.1 On-the-Fly Checking Versus End-of-Test Case Checking314
- 8.1.2 Pregenerated Test Cases Versus On-the-Fly Generated Test Cases321
- 8.1.3 Applying the Checking Strategies to Calc2322
- 8.2 DEBUG334
- 8.2.1 Debug Process336
- 8.2.2 How Different Types of Test Benches Affect Debug349
- 8.3 SUMMARY352
- 8.4 EXERCISES353
- CHAPTER 9: PERVASIVE FUNCTION VERIFICATION355
- 9.1 SYSTEM RESET AND BRING-UP356
- 9.1.1 Reset Line Initialization357
- 9.1.2 Scan Initialization361
- 9.1.3 Testability and Built-In Self-Test363
- 9.2 ERROR AND DEGRADED MODE HANDLING368
- 9.2.1 Verifying Error Detection368
- 9.2.2 Verifying Self-Healing Hardware372
- 9.3 VERIFYING HARDWARE DEBUG ASSISTS380
- 9.3.1 Verifying Scan Ring Dumps381
- 9.4 LOW-POWER MODE VERIFICATION384
- 9.4.1 Power Savings Through Disabling Functional Units385
- 9.4.2 Power Savings Through Cycle-Time Degradation387
- 9.5 SUMMARY389
- 9.6 EXERCISES389
- CHAPTER 10: RE-USE STRATEGIES AND SYSTEM SIMULATION391
- 10.1 RE-USE STRATEGIES392
- 10.1.1 Guidelines for Re-Use395
- 10.1.2 Horizontal Re-Use403
- 10.1.3 Vertical Re-Use404
- 10.1.4 Applying Re-Use to Calc2405
- 10.1.5 Assertion Re-Use410
- 10.2 SYSTEM SIMULATION412
- 10.2.1 Systems Test Bench412
- 10.2.2 Connectivity and Interaction of Units414
- 10.2.3 Verification Challenges in a Re-Usable IP World418
- 10.3 BEYOND GENERAL-PURPOSE LOGIC SIMULATION420
- 10.3.1 Acceleration421
- 10.3.2 Emulation427
- 10.3.3 Hardware/Software Co-verification428
- 10.3.4 Co-simulation430
- 10.4 SUMMARY434
- 10.5 EXERCISES435
- PART III: FORMAL VERIFICATION437
- CHAPTER 11: INTRODUCTION TO FORMAL VERIFICATION439
- 11.1 FOUNDATIONS440
- 11.1.1 Design Correctness and Specifications441
- 11.1.2 Computational Complexity443
- 11.1.3 The Myth of Linear Scaling of Simulation445
- 11.1.4 Mathematical Proof Methods in FV446
- 11.2 FORMAL BOOLEAN EQUIVALENCE CHECKING448
- 11.2.1 The Role of Equivalence Checking in the VLSI Design Flow449
- 11.2.2 Main Elements of an Equivalence Checker Tool450
- 11.2.3 Sequential and Combinational BEC451
- 11.2.4 Core Algorithms for Combinational Equivalence Checking454
- 11.2.5 Blueprint of a Modern Equivalence Checking Tool465
- 11.3 FUNCTIONAL FV„PROPERTY CHECKING467
- 11.3.1 Property Checking Versus Sequential Equivalence Checking468
- 11.3.2 The Myth of Complete Verification With FV470
- 11.3.3 Properties for an Example Design471
- 11.3.4 DUV Drivers for FV476
- 11.3.5 State Space Traversal and Temporal Logic479
- 11.3.6 Functional FV Tool Flow483
- 11.4 SUMMARY484
- 11.5 EXERCISES485
- CHAPTER 12: USING FORMAL VERIFICATION487
- 12.1 PROPERTY SPECIFICATION USING AN HDL LIBRARY488
- 12.1.1 The OVL489
- 12.1.2 Using OVL to Specify Properties495
- 12.2 THE PROPERTY SPECIFICATION LANGUAGE PSL499
- 12.2.1 Overview500
- 12.2.2 The Boolean Layer of PSL501
- 12.2.3 The Temporal Layer of PSL504
- 12.2.4 The Verification Layer of PSL508
- 12.2.5 The Modeling Layer of PSL511
- 12.2.6 Using PSL to Specify Properties512
- 12.2.7 Advanced PSL Topics and Caveats514
- 12.3 PROPERTY CHECKING USING FV521
- 12.3.1 Property Re-Use Between Simulation and FV521
- 12.3.2 Model Compilation522
- 12.3.3 Formal Functional Verification Algorithms523
- 12.3.4 Solutions to Address the Problem of State Space Explosion527
- 12.3.5 Semi-Formal Verification530
- 12.3.6 EDA Vendors Supplying Formal and Semi-Formal Verification Tools532
- 12.4 SUMMARY532
- 12.5 EXERCISES533
- PART IV: COMPREHENSIVE VERIFICATION537
- CHAPTER 13: COMPLETING THE VERIFICATION CYCLE539
- 13.1 REGRESSION540
- 13.1.1 Regression in the Verification Flow540
- 13.1.2 Regression Quality542
- 13.1.3 Regression Efficiency543
- 13.2 PROBLEM TRACKING548
- 13.3 TAPE-OUT READINESS552
- 13.3.1 Metrics552
- 13.3.2 Completion Criteria557
- 13.4 ESCAPE ANALYSIS559
- 13.4.1 Individual Bug Analysis561
- 13.4.2 Escape Examples569
- 13.4.3 Escape Analysis Trends572
- 13.5 SUMMARY575
- 13.6 EXERCISES577
- CHAPTER 14: ADVANCED VERIFICATION TECHNIQUES579
- 14.1 SAVE VERIFICATION CYCLES„BOOTSTRAPPING THE VERIFICATION PROCESS580
- 14.1.1 Separating Power-On-Reset and Mainline Verification580
- 14.1.2 Bootstrapping the DUV Into High-Potential States583
- 14.1.3 Manipulating the DUV Specification Provoking States of Resource Conflict585
- 14.2 HIGH-LEVEL MODELING: CONCEPTS586
- 14.2.1 Applications of the High-Level Model587
- 14.2.2 High-Level Modeling Styles590
- 14.3 COVERAGE-DIRECTED GENERATION595
- 14.4 SUMMARY598
- 14.5 EXERCISES599
- PART V: CASE STUDIES601
- CHAPTER 15: CASE STUDIES603
- 15.1 THE LINE DELETE ESCAPE603
- 15.1.1 Background603
- 15.1.2 The Verification Environments605
- 15.1.3 The Escape607
- 15.2 BRANCH HISTORY TABLE608
- 15.2.1 Background608
- 15.2.2 BHT Purpose and Logic Design609
- 15.2.3 BHT Verification614
- 15.2.4 Results624
- 15.3 NETWORK PROCESSOR624
- 15.3.1 System Overview625
- 15.3.2 Verification Effort627
- 15.3.3 Results638
- 15.4 SUMMARY639
- VERIFICATION GLOSSARY641
- REFERENCES657
- SUBJECT INDEX663
One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.
As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text.
A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.
* Comprehensive overview of the complete verification cycle
* Combines industry experience with a strong emphasis on functional verification fundamentals
* Includes real-world case studies and downloadable software implementations of key examples from the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys)
As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text.
A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.
* Comprehensive overview of the complete verification cycle
* Combines industry experience with a strong emphasis on functional verification fundamentals
* Includes real-world case studies and downloadable software implementations of key examples from the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys)