Customizable Embedded Processors: Design Technologies and Applications
Regular price
30.000 KD
inc. VAT
Couldn't load pickup availability
Table of contents
- Copyright Pagevi
- Contentsix
- In Praise of Customizable Embedded Processorsi
- List of Contributorsxix
- About the Editorsxxvii
- Part I: Opportunities and Challenges1
- Chapter 1. From Prêt-à-Porter to Tailor-Made3
- 1.1 The Call for Flexibility4
- 1.2 Cool Chips for Shallow Pockets5
- 1.3 A Million Processors for the Price of One?5
- 1.4 Processors Coming of Age7
- 1.5 This Book7
- 1.6 Travel Broadens the Mind9
- Chapter 2. Opportunities for Application-Specific Processors: The Case of Wireless Communications11
- 2.1 Future Mobile Communication Systems12
- 2.2 Heterogeneous MPSoC for Digital Receivers14
- 2.3 ASIP Design26
- Chapter 3. Customizing Processors: Lofty Ambitions, Stark Realities39
- 3.1 The CFPŽ project at HP Labs41
- 3.2 Searching for the Best Architecture Is Not a Machine-Only Endeavor45
- 3.3 Designing a CPU Core Still Takes a Very Long Time46
- 3.4 Don’t Underestimate Competitive Technologies48
- 3.5 Software Developers Don’t Always Help You49
- 3.6 The Embedded World Is Not Immune to Legacy Problems51
- 3.7 Customization Can Be Trouble52
- 3.8 Conclusions53
- Part II: Aspects of Processor Customization57
- Chapter 4. Architecture Description Languages59
- 4.1 ADLs and other languages60
- 4.2 Survey of Contemporary ADLs62
- 4.3 Conclusions75
- Chapter 5. C Compiler Retargeting77
- 5.1 Compiler Construction Background79
- 5.2 Approaches to Retargetable Compilation91
- 5.3 Processor Architecture Exploration98
- 5.4 C Compiler Retargeting in the LISATek Platform104
- 5.5 Summary and Outlook113
- Chapter 6. Automated Processor Configuration and Instruction Extension117
- 6.1 Automation Is Essential for ASIP Proliferation118
- 6.2 The Tensilica Xtensa LX Configurable Processor119
- 6.3 Generating ASIPs Using Xtensa121
- 6.4 Automatic Generation of ASIP Specifications123
- 6.5 Coding an Application for Automatic ASIP Generation125
- 6.6 XPRES Benchmarking Results126
- 6.7 Techniques for ASIP Generation128
- 6.8 Exploring the Design Space136
- 6.9 Evaluating Xpres Estimation Methods137
- 6.10 Conclusions and Future of the Technology142
- Chapter 7. Automatic Instruction-Set Extensions145
- 7.1 Beyond Traditional Compilers145
- 7.2 Building Block for Instruction Set Extension147
- 7.3 Heuristics160
- 7.4 State-Holding Instruction-Set Extensions163
- 7.5 Exploiting Pipelining to Relax I/O Constraints170
- 7.6 Conclusions and Further Challenges183
- Chapter 8. Challenges to Automatic Customization185
- 8.1 The ARCompactTM Instruction Set Architecture186
- 8.2 Microarchitecture Challenges191
- 8.3 Case Study„Entropy Decoding193
- 8.4 Limitations of Automated Extension203
- 8.5 The Benefits of Architecture Extension205
- 8.6 Conclusions207
- Chapter 9. Coprocessor Generation from Executable Code209
- 9.1 Introduction209
- 9.2 User Level Flow210
- 9.3 Integration with Embedded Software214
- 9.4 Coprocessor Architecture215
- 9.5 ILP Extraction Challenges218
- 9.6 Internal Tool Flow220
- 9.7 Code Mapping Approach225
- 9.8 Synthesizing Coprocessor Architectures228
- 9.9 A Real-World Example229
- 9.10 Summary231
- Chapter 10. Datapath Synthesis233
- 10.1 Introduction233
- 10.2 Custom Instruction Selection234
- 10.3 Theoretical Preliminaries236
- 10.4 Minimum Area-Cost Acyclic Common Supergraph Heuristic238
- 10.5 Multiplexer Insertion246
- 10.6 Datapath Synthesis249
- 10.7 Experimental Results250
- 10.8 Conclusion255
- Chapter 11. Instruction Matching and Modeling257
- 11.1 Matching Instructions259
- 11.2 Modeling268
- 11.3 Conclusions277
- Chapter 12. Processor Verification281
- 12.1 Motivation281
- 12.2 Overview of Verification Approaches282
- 12.3 Formal Verification of a RISC CPU285
- 12.4 Verification Challenges in Customizable and Configurable Embedded Processors293
- 12.5 Verification of Processor Peripherals294
- 12.6 Conclusions302
- Chapter 13. Sub-RISC Processors303
- 13.1 Concurrent Architectures, Concurrent Applications303
- 13.2 Motivating Sub-RISC PEs306
- 13.3 Designing TIPI Processing Elements316
- 13.4 Deploying Applications with Cairn321
- 13.5 IPv4 Forwarding Design Example327
- 13.6 Performance Results331
- 13.7 Conclusion335
- Part III: Case Studies337
- Chapter 14. Application Specific Instruction Set Processor for UMTS-FDD Cell Search339
- 14.1 ASIP on Wireless Modem Design340
- 14.2 Functionality of Cell Search ASIP346
- 14.3 Cell Search ASIP Design and Verification348
- 14.4 Results356
- 14.5 Summary and Conclusions359
- Chapter 15. Hardware/Software Tradeoffs for Advanced 3G Channel Decoding361
- 15.1 Channel Decoding for 3G Systems and Beyond361
- 15.2 Design Space366
- 15.3 Programmable Solutions368
- 15.4 Multiprocessor Architectures374
- 15.5 Conclusion379
- Chapter 16. Application Code Profiling and ISA Synthesis on MIPS32381
- 16.1 Profiling of Application Source Code384
- 16.2 Semi-Automatic ISA Extension Synthesis394
- 16.3 Summary and Outlook422
- Chapter 17. Designing Soft Processors for FPGAs425
- 17.1 Overview425
- 17.2 MicroBlaze Soft Processor Architecture430
- 17.3 Discussion of Architectural Design Tradeoffs in MicroBlaze432
- 17.4 Conclusions441
- Chapter References443
- Bibliography465
- Index485
Customizable processors have been described as the next natural step in the evolution of the microprocessor business: a step in the life of a new technology where top performance alone is no longer sufficient to guarantee market success. Other factors become fundamental, such as time to market, convenience, energy efficiency, and ease of customization.
This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include “as is in their products; but rather, to build sound methodologies to tailor-fit processors to the specific needs of such products. This book addresses the goal of maintaining a very large family of processors, with a wide range of features, at a cost comparable to that of maintaining a single processor.
· First book to present comprehensively the major ASIP design methodologies and tools without any particular bias.
· Written by most of the pioneers and top international experts of this young domain.
· Unique mix of management perspective, technical detail, research outlook, and practical implementation.
This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include “as is in their products; but rather, to build sound methodologies to tailor-fit processors to the specific needs of such products. This book addresses the goal of maintaining a very large family of processors, with a wide range of features, at a cost comparable to that of maintaining a single processor.
· First book to present comprehensively the major ASIP design methodologies and tools without any particular bias.
· Written by most of the pioneers and top international experts of this young domain.
· Unique mix of management perspective, technical detail, research outlook, and practical implementation.