Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools
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Table of contents
- Cover
- About the Authorsix
- Forewordxi
- Contentsxiii
- Prefacexxvii
- Content and Structurexxviii
- The VEX (VLIW Example) Computing Systemxxx
- Audiencexxx
- Cross-cutting Topicsxxxi
- How to Read This Bookxxxii
- Figure Acknowledgmentsxxxiv
- Acknowledgmentsxxxv
- CHAPTER 1 An Introduction to Embedded Processing1
- 1.1 What Is Embedded Computing?3
- 1.1.1 Attributes of Embedded Devices4
- 1.1.2 Embedded Is Growing5
- 1.2 Distinguishing Between Embedded and General-Purpose Computing6
- 1.2.1 The Run One Program OnlyŽ Phenomenon8
- 1.2.2 Backward and Binary Compatibility9
- 1.2.3 Physical Limits in the Embedded Domain10
- 1.3 Characterizing Embedded Computing11
- 1.3.1 Categorization by Type of Processing Engine12
- 1.3.2 Categorization by Application Area17
- 1.3.3 Categorization by Workload Differences22
- 1.4 Embedded Market Structure23
- 1.4.1 The Market for Embedded Processor Cores24
- 1.4.2 Business Model of Embedded Processors25
- 1.4.3 Costs and Product Volume26
- 1.4.4 Software and the Embedded Software Market28
- 1.4.5 Industry Standards28
- 1.4.6 Product Life Cycle30
- 1.4.7 The Transition to SoC Design31
- 1.4.8 The Future of Embedded Systems36
- 1.5 Further Reading38
- 1.6 Exercises40
- CHAPTER 2 An Overview of VLIW and ILP45
- 2.1 Semantics and Parallelism46
- 2.1.1 Baseline: Sequential Program Semantics46
- 2.1.2 Pipelined Execution, Overlapped Execution, and Multiple Execution Units47
- 2.1.3 Dependence and Program Rearrangement51
- 2.1.4 ILP and Other Forms of Parallelism52
- 2.2 Design Philosophies54
- 2.2.1 An Illustration of Design Philosophies: RISC Versus CISC56
- 2.2.2 First Definition of VLIW57
- 2.2.3 A Design Philosophy: VLIW59
- 2.3 Role of the Compiler63
- 2.3.1 The Phases of a High-Performance Compiler63
- 2.3.2 Compiling for ILP and VLIW65
- 2.4 VLIW in the Embedded and DSP Domains69
- 2.5 Historical Perspective and Further Reading71
- 2.5.1 ILP Hardware in the 1960s and 1970s71
- 2.5.2 The Development of ILP Code Generation in the 1980s73
- 2.5.3 VLIW Development in the 1980s76
- 2.5.4 ILP in the 1990s and 2000s77
- 2.6 Exercises78
- CHAPTER 3 An Overview of ISA Design83
- 3.1 Overview: What to Hide84
- 3.1.1 Architectural State: Memory and Registers84
- 3.1.2 Pipelining and Operational Latency85
- 3.1.3 Multiple Issue and Hazards86
- 3.1.4 Exception and Interrupt Handling89
- 3.1.5 Discussion90
- 3.2 Basic VLIW Design Principles91
- 3.2.1 Implications for Compilers and Implementations92
- 3.2.2 Execution Model Subtleties93
- 3.3 Designing a VLIW ISA for Embedded Systems95
- 3.3.1 Application Domain96
- 3.3.2 ILP Style98
- 3.3.3 Hardware/Software Tradeoffs100
- 3.4 Instruction-set Encoding101
- 3.4.1 A Larger Definition of Architecture101
- 3.4.2 Encoding and Architectural Style105
- 3.5 VLIW Encoding112
- 3.5.1 Operation Encoding113
- 3.5.2 Instruction Encoding113
- 3.5.3 Dispatching and Opcode Subspaces117
- 3.6 Encoding and Instruction-set Extensions119
- 3.7 Further Reading121
- 3.8 Exercises121
- CHAPTER 4 Architectural Structures in ISA Design125
- 4.1 The Datapath127
- 4.1.1 Location of Operands and Results127
- 4.1.2 Datapath Width127
- 4.1.3 Operation Repertoire129
- 4.1.4 Micro-SIMD Operations139
- 4.1.5 Constants144
- 4.2 Registers and Clusters144
- 4.2.1 Clustering145
- 4.2.2 Heterogeneous Register Files149
- 4.2.3 Address and Data Registers149
- 4.2.4 Special Register File Features150
- 4.3 Memory Architecture151
- 4.3.1 Addressing Modes152
- 4.3.2 Access Sizes153
- 4.3.3 Alignment Issues153
- 4.3.4 Caches and Local Memories154
- 4.3.5 Exotic Addressing Modes for Embedded Processing156
- 4.4 Branch Architecture156
- 4.4.1 Unbundling Branches158
- 4.4.2 Multiway Branches160
- 4.4.3 Multicluster Branches161
- 4.4.4 Branches and Loops162
- 4.5 Speculation and Predication163
- 4.5.1 Speculation163
- 4.5.2 Predication168
- 4.6 System Operations173
- 4.7 Further Reading174
- 4.8 Exercises175
- CHAPTER 5 Microarchitecture Design179
- 5.1 Register File Design182
- 5.1.1 Register File Structure182
- 5.1.2 Register Files, Technology, and Clustering183
- 5.1.3 Separate Address and Data Register Files184
- 5.1.4 Special Registers and Register File Features186
- 5.2 Pipeline Design186
- 5.2.1 Balancing a Pipeline187
- 5.3 VLIW Fetch, Sequencing, and Decoding191
- 5.3.1 Instruction Fetch191
- 5.3.2 Alignment and Instruction Length192
- 5.3.3 Decoding and Dispersal194
- 5.3.4 Decoding and ISA Extensions195
- 5.4 The Datapath195
- 5.4.1 Execution Units197
- 5.4.2 Bypassing and Forwarding Logic200
- 5.4.3 Exposing Latencies202
- 5.4.4 Predication and Selects204
- 5.5 Memory Architecture206
- 5.5.1 Local Memory and Caches206
- 5.5.2 Byte Manipulation209
- 5.5.3 Addressing, Protection, and Virtual Memory210
- 5.5.4 Memories in Multiprocessor Systems211
- 5.5.5 Memory Speculation213
- 5.6 The Control Unit214
- 5.6.1 Branch Architecture214
- 5.6.2 Predication and Selects215
- 5.6.3 Interrupts and Exceptions216
- 5.6.4 Exceptions and Pipelining218
- 5.7 Control Registers221
- 5.8 Power Considerations221
- 5.8.1 Energy Efficiency and ILP222
- 5.9 Further Reading225
- 5.10 Exercises227
- CHAPTER 6 System Design and Simulation231
- 6.1 System-on-a-Chip (SoC)231
- 6.1.1 IP Blocks and Design Reuse232
- 6.1.2 Design Flows236
- 6.1.3 SoC Buses239
- 6.2 Processor Cores and SoC245
- 6.2.1 Nonprogrammable Accelerators246
- 6.2.2 Multiprocessing on a Chip250
- 6.3 Overview of Simulation254
- 6.3.1 Using Simulators256
- 6.4 Simulating a VLIW Architecture257
- 6.4.1 Interpretation258
- 6.4.2 Compiled Simulation259
- 6.4.3 Dynamic Binary Translation268
- 6.4.4 Trace-driven Simulation270
- 6.5 System Simulation271
- 6.5.1 I/O and Concurrent Activities272
- 6.5.2 Hardware Simulation272
- 6.5.3 Accelerating Simulation275
- 6.6 Validation and Verification276
- 6.6.1 Co-simulation278
- 6.6.2 Simulation, Verification, and Test279
- 6.7 Further Reading282
- 6.8 Exercises284
- CHAPTER 7 Embedded Compiling and Toolchains287
- 7.1 What Is Important in an ILP Compiler?287
- 7.2 Embedded Cross-Development Toolchains290
- 7.2.1 Compiler291
- 7.2.2 Assembler292
- 7.2.3 Libraries294
- 7.2.4 Linker296
- 7.2.5 Post-link Optimizer297
- 7.2.6 Run-time Program Loader297
- 7.2.7 Simulator299
- 7.2.8 Debuggers and Monitor ROMs300
- 7.2.9 Automated Test Systems301
- 7.2.10 Profiling Tools302
- 7.2.11 Binary Utilities302
- 7.3 Structure of an ILP Compiler302
- 7.3.1 Front End304
- 7.3.2 Machine-independent Optimizer304
- 7.3.3 Back End: Machine-specific Optimizations306
- 7.4 Code Layout306
- 7.4.1 Code Layout Techniques306
- 7.5 Embedded-Specific Tradeoffs for Compilers311
- 7.5.1 Space, Time, and Energy Tradeoffs312
- 7.5.2 Power-specific Optimizations315
- 7.6 DSP-Specific Compiler Optimizations320
- 7.6.1 Compiler-visible Features of DSPs322
- 7.6.2 Instruction Selection and Scheduling325
- 7.6.3 Address Computation and Offset Assignment327
- 7.6.4 Local Memories327
- 7.6.5 Register Assignment Techniques328
- 7.6.6 Retargetable DSP and ASIP Compilers329
- 7.7 Further Reading332
- 7.8 Exercises333
- CHAPTER 8 Compiling for VLIWs and ILP337
- 8.1 Profiling338
- 8.1.1 Types of Profiles338
- 8.1.2 Profile Collection341
- 8.1.3 Synthetic Profiles (Heuristics in Lieu of Profiles)341
- 8.1.4 Profile Bookkeeping and Methodology342
- 8.1.5 Profiles and Embedded Applications342
- 8.2 Scheduling343
- 8.2.1 Acyclic Region Types and Shapes345
- 8.2.3 Schedule Construction357
- 8.2.4 Resource Management During Scheduling368
- 8.2.5 Loop Scheduling371
- 8.2.6 Clustering380
- 8.3 Register Allocation382
- 8.3.1 Phase-ordering Issues383
- 8.4 Speculation and Predication385
- 8.4.1 Control and Data Speculation385
- 8.4.2 Predicated Execution386
- 8.4.3 Prefetching389
- 8.4.4 Data Layout Methods390
- 8.4.5 Static and Hybrid Branch Prediction390
- 8.5 Instruction Selection390
- 8.6 Further Reading391
- 8.7 Exercises395
- CHAPTER 9 The Run-time System399
- 9.1 Exceptions, Interrupts, and Traps400
- 9.1.1 Exception Handling400
- 9.2 Application Binary Interface Considerations402
- 9.2.1 Loading Programs404
- 9.2.2 Data Layout406
- 9.2.3 Accessing Global Data407
- 9.2.4 Calling Conventions409
- 9.2.5 Advanced ABI Topics412
- 9.3 Code Compression415
- 9.3.1 Motivations416
- 9.3.2 Compression and Information Theory417
- 9.3.3 Architectural Compression Options417
- 9.3.4 Compression Methods420
- 9.4 Embedded Operating Systems427
- 9.4.1 TraditionalŽ OS Issues Revisited427
- 9.4.2 Real-time Systems428
- 9.4.3 Multiple Flows of Control431
- 9.4.4 Market Considerations433
- 9.4.5 Downloadable Code and Virtual Machines436
- 9.5 Multiprocessing and Multithreading438
- 9.5.1 Multiprocessing in the Embedded World438
- 9.5.2 Multiprocessing and VLIW439
- 9.6 Further Reading440
- 9.7 Exercises441
- CHAPTER 10 Application Design and Customization443
- 10.1 Programming Language Choices443
- 10.1.1 Overview of Embedded Programming Languages444
- 10.1.2 Traditional C and ANSI C445
- 10.1.3 C++ and Embedded C++447
- 10.1.4 Matlab450
- 10.1.5 Embedded Java452
- 10.1.6 C Extensions for Digital Signal Processing456
- 10.1.7 Pragmas, Intrinsics, and Inline Assembly Language Code462
- 10.2 Performance, Benchmarking, and Tuning465
- 10.2.1 Importance and Methodology465
- 10.2.2 Tuning an Application for Performance466
- 10.2.3 Benchmarking473
- 10.3 Scalability and Customizability475
- 10.3.1 Scalability and Architecture Families476
- 10.3.2 Exploration and Scalability477
- 10.3.3 Customization478
- 10.3.4 Reconfigurable Hardware480
- 10.3.5 Customizable Processors and Tools481
- 10.3.6 Tools for Customization483
- 10.3.7 Architecture Exploration487
- 10.4 Further Reading489
- 10.5 Exercises490
- CHAPTER 11 Application Areas493
- 11.1 Digital Printing and Imaging493
- 11.1.1 Photo Printing Pipeline495
- 11.1.2 Implementation and Performance501
- 11.2 Telecom Applications505
- 11.2.1 Voice Coding506
- 11.2.2 Multiplexing509
- 11.2.3 The GSM Enhanced Full-rate Codec510
- 11.3 Other Application Areas514
- 11.3.1 Digital Video515
- 11.3.2 Automotive518
- 11.3.3 Hard Disk Drives522
- 11.3.4 Networking and Network Processors528
- 11.4 Further Reading535
- 11.5 Exercises537
- APPENDIX A The VEX System539
- A.1 The VEX Instruction-set Architecture540
- A.1.1 VEX Assembly Language Notation541
- A.1.2 Clusters542
- A.1.3 Execution Model544
- A.1.4 Architecture State545
- A.1.5 Arithmetic and Logic Operations545
- A.1.6 Intercluster Communication549
- A.1.7 Memory Operations550
- A.1.8 Control Operations552
- A.1.9 Structure of the Default VEX Cluster554
- A.1.10 VEX Semantics556
- A.2 The VEX Run-time Architecture558
- A.2.1 Data Allocation and Layout559
- A.2.2 Register Usage560
- A.2.3 Stack Layout and Procedure Linkage560
- A.3 The VEX C Compiler566
- A.3.1 Command Line Options568
- A.3.2 Compiler Pragmas576
- A.3.3 Inline Expansion583
- A.3.4 Machine Model Parameters585
- A.3.5 Custom Instructions586
- A.4 Visualization Tools588
- A.5 The VEX Simulation System589
- A.5.1 gprof Support591
- A.5.2 Simulating Custom Instructions594
- A.5.3 Simulating the Memory Hierarchy595
- A.6 Customizing the VEX Toolchain596
- A.6.1 Clusters596
- A.6.2 Machine Model Resources597
- A.6.3 Memory Hierarchy Parameters599
- A.7 Examples of Tool Usage599
- A.7.1 Compile and Run599
- A.7.2 Profiling602
- A.7.3 Custom Architectures603
- A.8 Exercises605
- APPENDIX B Glossary607
- APPENDIX C Bibliography631
- Index661
The fact that there are more embedded computers than general-purpose computers and that we are impacted by hundreds of them every day is no longer news. What is news is that their increasing performance requirements, complexity and capabilities demand a new approach to their design.
Fisher, Faraboschi, and Young describe a new age of embedded computing design, in which the processor is central, making the approach radically distinct from contemporary practices of embedded systems design. They demonstrate why it is essential to take a computing-centric and system-design approach to the traditional elements of nonprogrammable components, peripherals, interconnects and buses. These elements must be unified in a system design with high-performance processor architectures, microarchitectures and compilers, and with the compilation tools, debuggers and simulators needed for application development.
In this landmark text, the authors apply their expertise in highly interdisciplinary hardware/software development and VLIW processors to illustrate this change in embedded computing. VLIW architectures have long been a popular choice in embedded systems design, and while VLIW is a running theme throughout the book, embedded computing is the core topic. Embedded Computing examines both in a book filled with fact and opinion based on the authors many years of R&D experience.
· Complemented by a unique, professional-quality embedded tool-chain on the authors' website, http://www.vliw.org/book
· Combines technical depth with real-world experience
· Comprehensively explains the differences between general purpose computing systems and embedded systems at the hardware, software, tools and operating system levels.
· Uses concrete examples to explain and motivate the trade-offs.
Fisher, Faraboschi, and Young describe a new age of embedded computing design, in which the processor is central, making the approach radically distinct from contemporary practices of embedded systems design. They demonstrate why it is essential to take a computing-centric and system-design approach to the traditional elements of nonprogrammable components, peripherals, interconnects and buses. These elements must be unified in a system design with high-performance processor architectures, microarchitectures and compilers, and with the compilation tools, debuggers and simulators needed for application development.
In this landmark text, the authors apply their expertise in highly interdisciplinary hardware/software development and VLIW processors to illustrate this change in embedded computing. VLIW architectures have long been a popular choice in embedded systems design, and while VLIW is a running theme throughout the book, embedded computing is the core topic. Embedded Computing examines both in a book filled with fact and opinion based on the authors many years of R&D experience.
· Complemented by a unique, professional-quality embedded tool-chain on the authors' website, http://www.vliw.org/book
· Combines technical depth with real-world experience
· Comprehensively explains the differences between general purpose computing systems and embedded systems at the hardware, software, tools and operating system levels.
· Uses concrete examples to explain and motivate the trade-offs.