Network Processor Design: Issues and Practices, Volume 2
Regular price
34.750 KD
inc. VAT
Couldn't load pickup availability
Table of contents
- Copyright Pageiv
- Contentsvii
- About the Editorsv
- Prefacexv
- Chapter 1. Network Processors: Themes and Challenges1
- 1.1 Technology2
- 1.2 Programming3
- 1.3 Applications5
- 1.4 Challenges and Conclusions6
- References7
- PART I: DESIGN PRINCIPLES9
- Chapter 2. A Programmable, Scalable Platform for Next-Generation Networking11
- 2.1 The Network Processor Architecture14
- 2.2 Processor Scheduling17
- 2.3 Fibre Channel/Infiniband Implementation21
- 2.4 Performance Simulation and Analysis23
- 2.5 Conclusions26
- Acknowledgments27
- References27
- Chapter 3. Power Considerations in Network Processor Design29
- 3.1 Computational Performance Model32
- 3.2 Power Model37
- 3.3 Performance Metrics42
- 3.4 Design Results43
- 3.5 Summary and Conclusions49
- Acknowledgments49
- References49
- Chapter 4. Worst-Case Execution Time Estimation for Hardware-Assisted Multithreaded Processors51
- 4.1 Background and Motivation53
- 4.2 Processing Throughput of a Single Thread of Execution55
- 4.3 Processing Throughput of Two Threads59
- 4.4 Processing Throughput of Four Threads69
- 4.5 Limitations and Future Work69
- 4.6 Conclusions71
- Acknowledgments72
- References72
- Chapter 5. Multiprocessor Scheduling in Processor-Based Router Platforms: Issues and Ideas75
- 5.1 Related Work and Concepts77
- 5.2 Issues in Using Pfair Schedulers in Routers84
- 5.3 Multiprocessor Scheduling in Routers: Key Ideas87
- 5.4 Experimental Evaluation94
- 5.5 Conclusions96
- Acknowledgments96
- References96
- Chapter 6. A Massively Multithreaded Packet Processor101
- 6.1 Random External Memory Accesses104
- 6.2 Processor/Memory Architectures105
- 6.3 The Tribe Microarchitecture107
- 6.4 Network Block120
- 6.5 Interconnect124
- 6.6 Project Status128
- 6.7 Conclusions129
- References131
- Chapter 7. Exploring Trade-Offs in Performance and Programmability of Processing Element Topologies133
- 7.1 Problem Identification134
- 7.2 Performance Modeling and Evaluation137
- 7.3 Topology Exploration for Performance Metrics146
- 7.4 Interrelation Between Programmability and Topologies152
- 7.5 Conclusions155
- Acknowledgments156
- References157
- Chapter 8. Packet Classification and Termination in a Protocol Processor159
- 8.1 Programmable Protocol Processor160
- 8.2 Control Memory Access Accelerator165
- 8.3 System Performance177
- 8.4 Conclusions179
- 8.5 Further Work179
- Acknowledgments179
- References180
- Chapter 9. NP-Click: A Programming Model for the Intel IXP1200181
- 9.1 Background182
- 9.2 Programming Models185
- 9.3 Description of NP-Click188
- 9.4 Results194
- 9.5 Summary and Conclusions198
- 9.6 Future Work199
- Acknowledgments200
- References200
- Chapter 10. NEPAL: A Framework for Efficiently Structuring Applications for Network Processors203
- 10.1 Modules206
- 10.2 NEPAL Design Flow208
- 10.3 Module Extraction from Sequential Binaries209
- 10.4 Dynamic Module Manager213
- 10.5 Discussion215
- 10.6 Experiments216
- 10.7 Related Work223
- 10.8 Conclusions224
- References225
- Chapter 11. Effcient and Faithful Performance Modeling for Network-Processor-Based System Designs227
- 11.1 Approaches to Performance Modeling229
- 11.2 Discrete-Event Simulation231
- 11.3 Application-Hardware Interface232
- 11.4 Modeling Memory Reference Behavior233
- 11.5 Time Synchronization234
- 11.6 Modeling Multiple Processors235
- 11.7 Using Countach for Modeling Network Servers236
- 11.8 Performance Evaluation238
- 11.9 Conclusions and Ongoing Work240
- References241
- Chapter 12. High-Speed Legitimacy-Based DDoS Packet Filtering with Network Processors: A Case Study243
- 12.1 Background: Legitimacy Tests and Legitimacy List Management246
- 12.2 Prototype Architecture on the Intel IXP1200 Network Processor254
- 12.3 Performance Analysis Experiments258
- 12.4 Performance Results260
- 12.5 Lessons Learned on Architectural Directions for Network Processors266
- 12.6 Conclusions and Future Work269
- Acknowledgments270
- References270
- Chapter 13. Directions in Packet Classification for Network Processors273
- 13.1 Problem Formulation275
- 13.2 IP Prefix Pair Analysis279
- 13.3 Transport-Level Field Analysis289
- 13.4 Implications292
- 13.5 Conclusions293
- Appendix: Derivation of a Tighter Bound on the Number of Partial Overlaps294
- References297
- PART II: PRACTICES299
- Chapter 14. Implementing High-Performance, High-Value Traffic Management Using Agere Network Process301
- 14.1 Implementing Traffic Management302
- 14.2 10-Gb/s System Solution304
- 14.3 5-Gb/s APP550 Solution320
- 14.4 Conclusions325
- References326
- Chapter 15. AMCC nPcore NISC Architecture327
- 15.1 The nPcore-based Architecture327
- 15.2 Software Architecture339
- 15.3 Conclusions341
- References342
- Chapter 16. Adaptable Bandwidth Allocation for QoS Support in Network Processors343
- 16.1 Background344
- 16.2 QoS Design for Network Processors350
- 16.3 IBM PowerNP QoS Support359
- 16.4 Conclusions362
- References362
- Chapter 17. IDT Network Search Engine with QDR LA-1 Interface365
- 17.1 NSE Device Description366
- 17.2 Development and System Support Tools372
- 17.3 Database Search Solutions, Analysis and Comparison375
- 17.4 Conclusion383
- References383
- Chapter 18. Implementing Voice over AAL2 on a Network Processor385
- 18.1 IXP2400 Network Processor386
- 18.2 Voice Service Requirements387
- 18.3 VoAAL2 Service387
- 18.4 Packet Processing in the VoAAL2 Application389
- 18.5 QoS Considerations391
- 18.6 VoAAL2 Application on IXP2400393
- 18.7 Challenges and Lessons Learned399
- 18.8 Conclusions402
- References403
- Chapter 19. Implementing QoS Mechanisms on the Motorola C-Port C-5e Network Processor405
- 19.1 The Motorola C-5e Network Processor406
- 19.2 Implementing ATM QoS407
- 19.3 Implementing diffserv416
- 19.4 Design Alternatives424
- 19.5 Conclusions425
- References426
- Chapter 20. A C-Based Programming Language for Multiprocessor Network SoC Architectures427
- 20.1 Software Design Considerations427
- 20.2 The Teja NP Software Platform428
- 20.3 The Teja C Programming Language429
- 20.4 Platform Support438
- 20.5 Conclusions441
- References442
- Index443
Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors.
Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service.
·Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Linköpings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington.
·Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.
Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service.
·Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Linköpings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington.
·Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.