Network Processor Design: Issues and Practices, Volume 3
Regular price
33.750 KD
inc. VAT
Couldn't load pickup availability
Table of contents
- Contentsvii
- About the Editorsv
- Prefacexv
- Chapter 1. Network Processors: New Horizons1
- 1.1 Architecture3
- 1.2 Tools and Techniques4
- 1.3 Applications5
- 1.4 Conclusions7
- References7
- Chapter 2. Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instructi9
- 2.1 Instruction Delivery in NP Data Processors11
- 2.2 Segmented Instruction Cache13
- 2.3 Experimental Evaluation17
- 2.4 Related Work29
- 2.5 Conclusions and Future Work30
- References30
- Chapter 3. Efficient Packet Classification with Digest Caches33
- 3.1 Related Work34
- 3.2 Our Approach35
- 3.3 Evaluation42
- 3.4 Hardware Overhead49
- 3.5 Conclusions51
- Acknowledgments52
- References52
- Chapter 4. Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Expre55
- 4.1 Interface Fundamentals and Comparison57
- 4.2 Modeling the Interfaces59
- 4.3 Architecture Evaluation68
- 4.4 Conclusions77
- Acknowledgments78
- References78
- Chapter 5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet81
- 5.1 Requirements on TCP Offload Solution83
- 5.2 Architecture of TOE Solution87
- 5.3 Performance Analysis95
- 5.4 Conclusions97
- Acknowledgments98
- References98
- Chapter 6. A Hardware Platform for Network Intrusion Detection and Prevention99
- 6.1 Design Rationales and Principles100
- 6.2 Prototype NNIDS on a Network Interface104
- 6.3 Evaluation and Results110
- 6.4 Conclusions115
- References116
- Chapter 7. Packet Processing on a SIMD Stream Processor119
- 7.1 Background: Stream Programs and Architectures120
- 7.2 AES Encryption122
- 7.3 IPv4 Forwarding131
- 7.4 Related Work139
- 7.5 Conclusions and Future Work140
- Acknowledgments142
- References142
- Chapter 8. A Programming Environment for Packet-Processing Systems: Design Considerations145
- 8.1 Problem Domain147
- 8.2 Shangri-La. A Programming Environment for Packet-Processing Systems 150150
- 8.3 Design Details and Challenges152
- 8.4 Conclusions168
- References169
- Chapter 9. RNOS„A Middleware Platform for Low-Cost Packet-Processing Devices173
- 9.1 Scenario174
- 9.2 Analysis Model of RNOS175
- 9.3 Implementation Model of RNOS187
- 9.4 Measurements and Comparison192
- 9.5 Conclusions and Outlook193
- Acknowledgments194
- References194
- Chapter 10. On the Feasibility of Using Network Processors for DNA Queries197
- 10.1 Architecture198
- 10.2 Implementation Details210
- 10.3 Results211
- 10.4 Related Work215
- 10.5 Conclusions216
- Acknowledgments217
- References217
- Chapter 11. Pipeline Task Scheduling on Network Processors219
- 11.1 The Pipeline Task Assignment Problem221
- 11.2 The Greedypipe Algorithm225
- 11.3 Pipeline Design with Greedypipe228
- 11.4 A Network Processor Problem232
- 11.5 Conclusions242
- Acknowledgments243
- References243
- Chapter 12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Mul245
- 12.1 Related Work247
- 12.2 Modeling Packet-Processing Systems249
- 12.3 Scheduling255
- 12.4 Mapping the Application to the System261
- 12.5 Estimating the Resource Consumption264
- 12.6 A Design Space Exploration Example268
- 12.7 Conclusions275
- Acknowledgments275
- References276
- Chapter 13. Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectu279
- 13.1 Related Work282
- 13.2 Application Analysis283
- 13.3 ADAG Clustering Using Maximum Local Ratio Cut287
- 13.4 ADAG Results291
- 13.5 Mapping Application DAGs to NP Architectures302
- 13.6 Conclusions306
- References306
- Index309
The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors.
Through chapters on hardware, software, performance and modeling, Volume 3 illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors.
Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.
*Investigates current applications of network processor technology at Intel; Infineon Technologies; and NetModule.
Presents current research in network processor design in three distinct areas:
*Architecture at Washington University, St. Louis; Oregon Health and Science University; University of Georgia; and North Carolina State University.
*Tools and Techniques at University of Texas, Austin; Academy of Sciences, China; University of Paderborn, Germany; and University of Massachusetts, Amherst.
*Applications at University of California, Berkeley; Universidad Complutense de Madrid, Spain; ETH Zurich, Switzerland; Georgia Institute of Technology; Vrije Universiteit, the Netherlands; and Universiteit Leiden, the Netherlands.
Through chapters on hardware, software, performance and modeling, Volume 3 illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors.
Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.
*Investigates current applications of network processor technology at Intel; Infineon Technologies; and NetModule.
Presents current research in network processor design in three distinct areas:
*Architecture at Washington University, St. Louis; Oregon Health and Science University; University of Georgia; and North Carolina State University.
*Tools and Techniques at University of Texas, Austin; Academy of Sciences, China; University of Paderborn, Germany; and University of Massachusetts, Amherst.
*Applications at University of California, Berkeley; Universidad Complutense de Madrid, Spain; ETH Zurich, Switzerland; Georgia Institute of Technology; Vrije Universiteit, the Netherlands; and Universiteit Leiden, the Netherlands.