Elsevier S & T

On-Chip Communication Architectures: System on Chip Interconnect

Pasricha, Sudeep; Dutt, Nikil

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Table of contents
  • On-Chip Communication Architectures: System on Chip Interconnectiii
  • Copyright Pageiv
  • Contentsv
  • Prefaceix
  • About the Authorsxiii
  • Acknowledgmentsxv
  • List of Contributorsxvii
  • CHAPTER 1 Introduction1
  • 1.1. Trends in System-On-Chip Design1
  • 1.2. Coping with Soc Design Complexity3
  • 1.3. ESL Design Flow4
  • 1.4. On-Chip Communication Architectures: A Quick Look6
  • 1.5. Book Outline12
  • CHAPTER 2 Basic Concepts of Bus-Based Communication Architectures17
  • 2.1. Terminology18
  • 2.2. Characteristics of Bus-Based Communication Architectures19
  • 2.3. Data Transfer Modes28
  • 2.4. Bus Topology Types33
  • 2.5. Physical Implementation of Bus Wires37
  • 2.6. Discussion: Buses in the DSM Era38
  • 2.7. Summary39
  • CHAPTER 3 On-Chip Communication Architecture Standards43
  • 3.1. Standard On-Chip Bus-Based Communication Architectures44
  • 3.2. Socket-Based On-Chip Bus Interface Standards88
  • 3.3. Discussion: Off-Chip Bus Architecture Standards96
  • 3.4. Summary97
  • CHAPTER 4 Models for Performance Exploration101
  • 4.1. Static Performance Estimation Models102
  • 4.2. Dynamic (Simulation-Based) Performance Estimation Models111
  • 4.3. Hybrid Communication Architecture Performance Estimation Approaches132
  • 4.4. Summary138
  • CHAPTER 5 Models for Power and Thermal Estimation143
  • 5.1. Bus Wire Power Models145
  • 5.2. Comprehensive Bus Architecture Power Models153
  • 5.3. Bus Wire Thermal Models167
  • 5.4. Discussion: PVT Variation-Aware Power Estimation174
  • 5.5. Summary179
  • CHAPTER 6 Synthesis of On-Chip Communication Architectures185
  • 6.1. Bus Topology Synthesis187
  • 6.2. Bus Protocol Parameter Synthesis196
  • 6.3. Bus Topology and Protocol Parameter Synthesis205
  • 6.4. Physical Implementation Aware Synthesis216
  • 6.5. Memory–Communication Architecture Co-synthesis230
  • 6.6. Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures240
  • 6.7. Summary243
  • CHAPTER 7 Encoding Techniques for On-Chip Communication Architectures253
  • 7.1. Techniques for Power Reduction255
  • 7.2. Techniques for Reducing Capacitive Crosstalk Delay278
  • 7.3. Techniques for Reducing Power and Capacitive Crosstalk Effects282
  • 7.4. Techniques for Reducing Inductive Crosstalk Effects284
  • 7.5. Techniques for Fault Tolerance and Reliability287
  • 7.6. Summary292
  • CHAPTER 8 Custom Bus-Based On-Chip Communication Architecture Design301
  • 8.1. Split Bus Architectures301
  • 8.2. Serial Bus Architectures309
  • 8.3. CDMA-Based Bus Architectures310
  • 8.4. Asynchronous Bus Architectures313
  • 8.5. Dynamically Reconfigurable Bus Architectures318
  • 8.6. Summary336
  • CHAPTER 9 On-Chip Communication Architecture Refinement and Interface Synthesis341
  • 9.1. On-Chip Communication Architecture Refinement343
  • 9.2. Interface Synthesis346
  • 9.3. Discussion: Interface Synthesis361
  • 9.4. Summary361
  • CHAPTER 10 Verification and Security Issues in On-Chip Communication Architecture Design367
  • 10.1. Verification of On-Chip Communication Protocols369
  • 10.2. Compliance Verification for IP Block Integration376
  • 10.3. Basic Concepts of SoC Security388
  • 10.4. Security Support in Standard Bus Protocols391
  • 10.5. Communication Architecture Enhancements for Improving SoC Security391
  • 10.6. Summary395
  • CHAPTER 11 Physical Design Trends for Interconnects403
  • 11.1. DSM Interconnect Design405
  • 11.2. Low Power, High Speed Circuit Design Techniques408
  • 11.3. Global Power Distribution Networks417
  • 11.4. Clock Distribution Networks421
  • 11.5. 3-D Interconnects427
  • 11.6. Summary and Concluding Remarks429
  • CHAPTER 12 Networks-On-Chip439
  • 12.1. Network Topology443
  • 12.2. Switching Strategies448
  • 12.3. Routing Algorithms451
  • 12.4. Flow Control454
  • 12.5. Clocking Schemes458
  • 12.6. Quality of Service459
  • 12.7. NoC Architectures459
  • 12.8. NoC Status and Open Problems464
  • 12.9. Summary466
  • CHAPTER 13 Emerging On-Chip Interconnect Technologies473
  • 13.1. Optical Interconnects474
  • 13.2. RF/Wireless Interconnects483
  • 13.3. CNT Interconnects490
  • 13.4. Summary501
  • Index509
  • A509
  • B510
  • C511
  • D512
  • E513
  • F514
  • G514
  • H514
  • I515
  • J515
  • K515
  • L515
  • M516
  • N516
  • O517
  • P517
  • Q518
  • R519
  • S519
  • T521
  • U521
  • V522
  • W522
  • X522
  • Z522
Book details
  • Vendor Elsevier S & T
  • SKU 9780123738929
  • ISBN-13 9780080558288
  • Author Pasricha, Sudeep; Dutt, Nikil
  • Category Technology & Engineering
  • Subject Microelectronics

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Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years