Principles and Practices of Interconnection Networks

Dally, William James; Towles, Brian Patrick

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Table of contents
  • Contentsvii
  • Acknowledgmentsxvii
  • Prefacexix
  • About the Authorsxxv
  • Chapter 1. Introduction to Interconnection Networks1
  • 1.1 Three Questions About Interconnection Networks2
  • 1.2 Uses of Interconnection Networks4
  • 1.3 Network Basics13
  • 1.4 History21
  • 1.5 Organization of this Book23
  • Chapter 2. A Simple Interconnection Network25
  • 2.1 Network Specifications and Constraints25
  • 2.2 Topology27
  • 2.3 Routing31
  • 2.4 Flow Control32
  • 2.5 Router Design33
  • 2.6 Performance Analysis36
  • 2.7 Exercises42
  • Chapter 3 .Topology Basics45
  • 3.1 Nomenclature46
  • 3.2 Traffic Patterns50
  • 3.3 Performance51
  • 3.4 Packaging Cost60
  • 3.5 Case Study: The SGI Origin 200064
  • 3.6 Bibliographic Notes69
  • 3.7 Exercises69
  • Chapter 4. Butterfly Networks75
  • 4.1 The Structure of Butterfly Networks75
  • 4.2 Isomorphic Butterflies77
  • 4.3 Performance and Packaging Cost78
  • 4.4 Path Diversity and Extra Stages81
  • 4.5 Case Study: The BBN Butterfly84
  • 4.6 Bibliographic Notes86
  • 4.7 Exercises86
  • Chapter 5. Torus Networks89
  • 5.1 The Structure of Torus Networks90
  • 5.2 Performance92
  • 5.3 Building Mesh and Torus Networks98
  • 5.4 Express Cubes100
  • 5.5 Case Study: The MIT J-Machine102
  • 5.6 Bibliographic Notes106
  • 5.7 Exercises107
  • Chapter 6. Non-Blocking Networks111
  • 6.1 Non-Blocking vs. Non-Interfering Networks112
  • 6.2 Crossbar Networks112
  • 6.3 Clos Networks116
  • 6.4 Beneˇs Networks134
  • 6.5 Sorting Networks135
  • 6.6 Case Study: The Velio VC2002 (Zeus) Grooming Switch137
  • 6.7 Bibliographic Notes142
  • 6.8 Exercises142
  • Chapter 7. Slicing and Dicing145
  • 7.1 Concentrators and Distributors146
  • 7.2 Slicing and Dicing149
  • 7.3 Slicing Multistage Networks153
  • 7.4 Case Study: Bit Slicing in the Tiny Tera155
  • 7.5 Bibliographic Notes157
  • 7.6 Exercises157
  • Chapter 8. Routing Basics159
  • 8.1 A Routing Example160
  • 8.2 Taxonomy of Routing Algorithms162
  • 8.3 The Routing Relation163
  • 8.4 Deterministic Routing164
  • 8.5 Case Study: Dimension-Order Routing in the Cray T3D168
  • 8.6 Bibliographic Notes170
  • 8.7 Exercises171
  • Chapter 9. Oblivious Routing173
  • 9.1 Valiant’s Randomized Routing Algorithm174
  • 9.2 Minimal Oblivious Routing176
  • 9.3 Load-Balanced Oblivious Routing180
  • 9.4 Analysis of Oblivious Routing180
  • 9.5 Case Study: Oblivious Routing in the Avici Terabit Switch Router(TSR)183
  • 9.6 Bibliographic Notes186
  • 9.7 Exercises187
  • Chapter 10. Adaptive Routing189
  • 10.1 Adaptive Routing Basics189
  • 10.2 Minimal Adaptive Routing192
  • 10.3 Fully Adaptive Routing193
  • 10.4 Load-Balanced Adaptive Routing195
  • 10.5 Search-Based Routing196
  • 10.6 Case Study: Adaptive Routing in the Thinking Machines CM-5196
  • 10.7 Bibliographic Notes201
  • 10.8 Exercises201
  • Chapter 11. Routing Mechanics203
  • 11.1 Table-Based Routing203
  • 11.2 Algorithmic Routing211
  • 11.3 Case Study: Oblivious Source Routing in the IBM Vulcan Network212
  • 11.4 Bibliographic Notes217
  • 11.5 Exercises217
  • Chapter 12. Flow Control Basics221
  • 12.1 Resources and Allocation Units222
  • 12.2 Bufferless Flow Control225
  • 12.3 Circuit Switching228
  • 12.4 Bibliographic Notes230
  • 12.5 Exercises230
  • Chapter 13. Buffered Flow Control233
  • 13.1 Packet-Buffer Flow Control234
  • 13.2 Flit-Buffer Flow Control237
  • 13.3 Buffer Management and Backpressure245
  • 13.4 Flit-Reservation Flow Control251
  • 13.5 Bibliographic Notes256
  • 13.6 Exercises256
  • Chapter 14. Deadlock and Livelock257
  • 14.1 Deadlock258
  • 14.2 Deadlock Avoidance263
  • 14.3 Adaptive Routing272
  • 14.4 Deadlock Recovery277
  • 14.5 Livelock279
  • 14.6 Case Study: Deadlock Avoidance in the Cray T3E279
  • 14.7 Bibliographic Notes281
  • 14.8 Exercises282
  • Chapter 15. Quality of Service285
  • 15.1 Service Classes and Service Contracts285
  • 15.2 Burstiness and Network Delays287
  • 15.3 Implementation of Guaranteed Services290
  • 15.4 Implementation of Best-Effort Services294
  • 15.5 Separation of Resources297
  • 15.6 Case Study: ATM Service Classes299
  • 15.7 Case Study: Virtual Networks in the Avici TSR300
  • 15.8 Bibliographic Notes302
  • 15.9 Exercises303
  • Chapter 16. Router Architecture305
  • 16.1 Basic Router Architecture305
  • 16.2 Stalls310
  • 16.3 Closing the Loop with Credits312
  • 16.4 Reallocating a Channel313
  • 16.5 Speculation and Lookahead316
  • 16.6 Flit and Credit Encoding319
  • 16.7 Case Study: The Alpha 21364 Router321
  • 16.8 Bibliographic Notes324
  • 16.9 Exercises324
  • Chapter 17. Router Datapath Components325
  • 17.1 Input Buffer Organization325
  • 17.2 Switches334
  • 17.3 Output Organization343
  • 17.4 Case Study: The Datapath of the IBM Colony Router344
  • 17.5 Bibliographic Notes347
  • 17.6 Exercises348
  • Chapter 18. Arbitration349
  • 18.1 Arbitration Timing349
  • 18.2 Fairness351
  • 18.3 Fixed Priority Arbiter352
  • 18.4 Variable Priority Iterative Arbiters354
  • 18.5 Matrix Arbiter358
  • 18.6 Queuing Arbiter360
  • 18.7 Exercises362
  • Chapter 19. Allocation363
  • 19.1 Representations363
  • 19.2 Exact Algorithms366
  • 19.3 Separable Allocators367
  • 19.4 Wavefront Allocator373
  • 19.5 Incremental vs. Batch Allocation376
  • 19.6 Multistage Allocation378
  • 19.7 Performance of Allocators380
  • 19.8 Case Study: The Tiny Tera Allocator383
  • 19.9 Bibliographic Notes385
  • 19.10 Exercises386
  • Chapter 20. Network Interfaces389
  • 20.1 Processor-Network Interface390
  • 20.2 Shared-Memory Interface394
  • 20.3 Line-Fabric Interface400
  • 20.4 Case Study: The MIT M-Machine Network Interface403
  • 20.5 Bibliographic Notes407
  • 20.6 Exercises408
  • Chapter 21. Error Control411
  • 21.1 Know Thy Enemy: Failure Modes and Fault Models411
  • 21.2 The Error Control Process: Detection, Containment, and Recovery414
  • 21.3 Link Level Error Control415
  • 21.4 Router Error Control421
  • 21.5 Network-Level Error Control422
  • 21.6 End-to-end Error Control423
  • 21.7 Bibliographic Notes423
  • 21.8 Exercises424
  • Chapter 22. Buses427
  • 22.1 Bus Basics428
  • 22.2 Bus Arbitration432
  • 22.3 High Performance Bus Protocol436
  • 22.4 From Buses to Networks441
  • 22.5 Case Study: The PCI Bus443
  • 22.6 Bibliographic Notes446
  • 22.7 Exercises446
  • Chapter 23. Performance Analysis449
  • 23.1 Measures of Interconnection Network Performance449
  • 23.2 Analysis460
  • 23.3 Valldation467
  • 23.4 Case Study: Efficiency and Loss in the BBN Monarch Network468
  • 23.5 Bibliographic Notes470
  • 23.6 Exercises471
  • Chapter 24. Simulation473
  • 24.1 Levels of Detail473
  • 24.2 Network Workloads475
  • 24.3 Simulation Measurements478
  • 24.4 Simulator Design484
  • 24.5 Bibliographic Notes491
  • 24.6 Exercises492
  • Chapter 25. Simulation Examples495
  • 25.1 Routing495
  • 25.2 Flow Control Performance500
  • 25.3 Fault Tolerance508
  • Appendix A. Nomenclature511
  • Appendix B. Glossary515
  • Appendix C. Network Simulator521
  • Bibliography523
  • Index539
  • Topology551
Book details
  • Vendor Elsevier S & T
  • SKU 9780122007514R150
  • ISBN-13 9780080497808
  • Author Dally, William James; Towles, Brian Patrick
  • Category Technology & Engineering
  • Subject Electrical

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One of the greatest challenges faced by designers of digital systems is optimizing the communication and interconnection between system components. Interconnection networks offer an attractive and economical solution to this communication crisis and are fast becoming pervasive in digital systems. Current trends suggest that this communication bottleneck will be even more problematic when designing future generations of machines. Consequently, the anatomy of an interconnection network router and science of interconnection network design will only grow in importance in the coming years.

This book offers a detailed and comprehensive presentation of the basic principles of interconnection network design, clearly illustrating them with numerous examples, chapter exercises, and case studies. It incorporates hardware-level descriptions of concepts, allowing a designer to see all the steps of the process from abstract design to concrete implementation.

·Case studies throughout the book draw on extensive author experience in designing interconnection networks over a period of more than twenty years, providing real world examples of what works, and what doesn't.

·Tightly couples concepts with implementation costs to facilitate a deeper understanding of the tradeoffs in the design of a practical network.

·A set of examples and exercises in every chapter help the reader to fully understand all the implications of every design decision.