Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
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Table of contents
- Cover
- Contentsv
- List of Contributorsxx
- Prefacexxiii
- Introductionxxv
- Part I: Reconfigurable Computing Hardware1
- Chapter 1. Device Architecture3
- 1.1 Logic„The Computational Fabric3
- 1.2 The Array and Interconnect6
- 1.3 Extending Logic12
- 1.4 Configuration16
- 1.5 Case Studies18
- 1.6 Summary26
- References27
- Chapter 2. Reconfigurable Computing Architectures29
- 2.1 Reconfigurable Processing Fabric Architectures30
- 2.2 RPF Integration into Traditional Computing Systems35
- 2.3 Summary and Future Work44
- References45
- Chapter 3. Reconfigurable Computing Systems47
- 3.1 Early Systems47
- 3.2 PAM, VCC, and Splash49
- 3.3 Small-Scale Reconfigurable Systems52
- 3.4 Circuit Emulation54
- 3.5 Accelerating Technology56
- 3.6 Reconfigurable Supercomputing59
- 3.7 Non-FPGA Research61
- 3.8 Other System Issues61
- 3.9 The Future of Reconfigurable Systems62
- References63
- Chapter 4. Reconfiguration Management65
- 4.1 Reconfiguration66
- 4.2 Configuration Architectures66
- 4.3 Managing the Reconfiguration Process76
- 4.4 Reducing Configuration Transfer Time80
- 4.5 Configuration Security82
- 4.6 Summary83
- References84
- Part II: Programming Reconfigurable Systems87
- Chapter 5. Compute Models and System Architectures91
- 5.1 Compute Models93
- 5.2 System Architectures107
- References125
- Chapter 6. Programming FPGA Applications in VHDL129
- 6.1 VHDL Programming130
- 6.2 Hardware Compilation Flow150
- 6.3 Limitations of VHDL153
- References153
- Chapter 7. Compiling C for Spatial Computing155
- 7.1 Overview of How C Code Runs on Spatial Hardware156
- 7.2 Automatic Compilation162
- 7.3 Uses and Variations of C Compilation to Hardware175
- 7.4 Summary180
- References180
- Chapter 8. Programming Streaming FPGA Applications Using Block Diagrams in Simulink183
- 8.1 Designing High-Performance Datapaths Using Stream-Based Operators184
- 8.2 An Image-Processing Design Driver185
- 8.3 Specifying Control in Simulink194
- 8.4 Component Reuse: Libraries of Simple and Complex Subsystems198
- 8.5 Summary201
- References202
- Chapter 9. Stream Computations Organized for Reconfigurable Execution203
- 9.1 Programming205
- 9.2 System Architecture and Execution Patterns208
- 9.3 Compilation212
- 9.4 Runtime213
- 9.5 Highlights217
- References217
- Chapter 10. Programming Data Parallel FPGA Applications Using the SIMD/Vector Model219
- 10.1 SIMD Computing on FPGAs: An Example219
- 10.2 SIMD Processing Architectures221
- 10.3 Data Parallel Languages222
- 10.4 Reconfigurable Computers for SIMD/Vector Processing223
- 10.5 Variations of SIMD/Vector Computing226
- 10.6 Pipelined SIMD/Vector Processing228
- 10.7 Summary229
- References230
- Chapter 11. Operating System Support for Reconfigurable Computing231
- 11.1 History232
- 11.2 Abstracted Hardware Resources234
- 11.3 Flexible Binding236
- 11.4 Scheduling239
- 11.5 Communication243
- 11.6 Synchronization248
- 11.7 Protection249
- 11.8 Summary252
- References252
- Chapter 12. The JHDL Design and Debug System255
- 12.1 JHDL Background and Motivation255
- 12.2 The JHDL Design Language257
- 12.3 The JHDL CAD System265
- 12.4 JHDL'S Hardware Mode268
- 12.5 Advanced JHDL Capabilities269
- 12.6 Summary272
- References273
- Part III: Mapping Designs to Reconfigurable Platforms275
- Chapter 13. Technology Mapping277
- 13.1 Structural Mapping Algorithms278
- 13.2 Integrated Mapping Algorithms284
- 13.3 Mapping Algorithms for Heterogeneous Resources289
- 13.4 Summary293
- References293
- FPGA Placement297
- Chapter 14. Placement for General-purpose FPGAs299
- 14.1 The FPGA Placement Problem299
- 14.2 Clustering304
- 14.3 Simulated Annealing for Placement306
- 14.4 Partition-Based Placement312
- 14.5 Analytic Placement315
- 14.6 Further Reading and Open Challenges316
- References316
- Chapter 15. Datapath Composition319
- 15.1 Fundamentals319
- 15.2 Tool Flow Overview323
- 15.3 The Impact of Device Architecture324
- 15.4 The Interface to Module Generators326
- 15.5 The Mapping329
- 15.6 Placement333
- 15.7 Compaction337
- 15.8 Summary and Future Work344
- References344
- Chapter 16. Specifying Circuit Layout on FPGAs347
- 16.1 The Problem347
- 16.2 Explicit Cartesian Layout Specification351
- 16.3 Algebraic Layout Specification352
- 16.4 Layout Verification for Parameterized Designs360
- 16.5 Summary362
- References363
- Chapter 17. PathFinder: A Negotiation-based, Performance-driven Router for FPGAs365
- 17.1 The History of PathFinder366
- 17.2 The PathFinder Algorithm367
- 17.3 Enhancements and Extensions to PathFinder374
- 17.4 Parallel PathFinder377
- 17.5 Other Applications of the PathFinder Algorithm379
- 17.6 Summary379
- References380
- Chapter 18. Retiming, Repipelining, and C-slow Retiming383
- 18.1 Retiming: Concepts, Algorithm, and Restrictions384
- 18.2 Repipelining and C-slow Retiming388
- 18.3 Implementations of Retiming393
- 18.4 Retiming on Fixed-Frequency FPGAs394
- 18.5 C-slowing as Multi-Threading395
- 18.6 Why Isn’t Retiming Ubiquitous?398
- References398
- Chapter 19. Configuration Bitstream Generation401
- 19.1 The Bitstream403
- 19.2 Downloading Mechanisms406
- 19.3 Software to Generate Configuration Data407
- 19.4 Summary409
- References409
- Chapter 20. Fast Compilation Techniques411
- 20.1 Accelerating Classical Techniques414
- 20.2 Alternative Algorithms422
- 20.3 Effect of Architecture427
- 20.4 Summary431
- References432
- Part IV: Application Development435
- Chapter 21. Implementing Applications with FPGAs439
- 21.1 Strengths and Weaknesses of FPGAs439
- 21.2 Application Characteristics and Performance441
- 21.3 General Implementation Strategies for FPGA-based Systems445
- 21.4 Implementing Arithmetic in FPGAs448
- 21.5 Summary452
- References452
- Chapter 22. Instance-specific Design455
- 22.1 Instance-specific Design455
- 22.2 Partial Evaluation462
- 22.3 Summary473
- References473
- Chapter 23. Precision Analysis for Fixed-point Computation475
- 23.1 Fixed-point Number System475
- 23.2 Peak Value Estimation478
- 23.3 Wordlength Optimization485
- 23.4 Summary498
- References499
- Chapter 24. Distributed Arithmetic503
- 24.1 Theory503
- 24.2 DA Implementation504
- 24.3 Mapping DA onto FPGAs507
- 24.4 Improving DA Performance508
- 24.5 An Application of DA on an FPGA511
- References511
- Chapter 25. Cordic Architectures for FPGA Computing513
- 25.1 Cordic Algorithm514
- 25.2 Architectural Design526
- 25.3 FPGA Implementation of Cordic Processors527
- 25.4 Summary534
- References535
- Chapter 26. Hardware/Software Partitioning539
- 26.1 The Trend Toward Automatic Partitioning540
- 26.2 Partitioning of Sequential Programs542
- 26.3 Partitioning of Parallel Programs557
- 26.4 Summary and Directions558
- References559
- Part V: Case Studies of FPGA Applications561
- Chapter 27. Spiht Image Compression565
- 27.1 Background565
- 27.2 Spiht Algorithm566
- 27.3 Design Considerations and Modifications571
- 27.4 Hardware Implementation580
- 27.5 Design Results587
- 27.6 Summary and Future Work588
- References589
- Chapter 28. Automatic Target Recognition Systems on Reconfigurable Devices591
- 28.1 Automatic Target Recognition Algorithms592
- 28.2 Dynamically Reconfigurable Designs594
- 28.3 Reconfigurable Static Design600
- 28.4 ATR Implementations604
- 28.5 Summary609
- References610
- Chapter 29. Boolean Satisfiability: Creating Solvers Optimized for Specific Problem Instances613
- 29.1 Boolean Satisfiability Basics613
- 29.2 Sat-solving Algorithms615
- 29.3 A Reconfigurable SAT Solver Generated According to an SAT Instance618
- 29.4 A Different Approach to Reduce Compilation Time and Improve Algorithm Efficiency627
- 29.5 Discussion633
- References635
- Chapter 30. Multi-FPGA Systems: Logic Emulation637
- 30.1 Background637
- 30.2 Uses of Logic Emulation Systems639
- 30.3 Types of Logic Emulation Systems640
- 30.4 Issues Related to Contemporary Logic Emulation650
- 30.5 The Need for Fast FPGA Mapping652
- 30.6 Case Study: The Virtualogic VLE Emulation System653
- 30.7 Future Trends666
- 30.8 Summary667
- References668
- Chapter 31. The Implications of Floating Point for FPGAs671
- 31.1 Why is Floating Point Difficult?671
- 31.2 Floating-point Application Case Studies679
- 31.3 Summary692
- References694
- Chapter 32. Finite Difference Time Domain: A Case Study Using FPGAs697
- 32.1 The FDTD Method697
- 32.2 FDTD Hardware Design Case Study707
- 32.3 Summary723
- References723
- Chapter 33. Evolvable FPGAs725
- 33.1 The Poe Model of Bioinspired Design Methodologies725
- 33.2 Artificial Evolution727
- 33.3 Evolvable Hardware729
- 33.4 Evolvable Hardware: A Taxonomy733
- 33.5 Evolvable Hardware Digital Platforms739
- 33.6 Conclusions and Future Directions745
- References747
- Chapter 34. Network Packet Processing in Reconfigurable Hardware753
- 34.1 Networking with Reconfigurable Hardware753
- 34.2 Network Protocol Processing757
- 34.3 Intrusion Detection and Prevention762
- 34.4 Semantic Processing767
- 34.5 Complete Networking System Issues770
- 34.6 Summary775
- References776
- Chapter 35. Active Pages:Memory-centric Computation779
- 35.1 Active Pages779
- 35.2 Performance Results781
- 35.3 Algorithmic Complexity786
- 35.4 Exploring Parallelism794
- 35.5 Defect Tolerance799
- 35.6 Related Work801
- 35.7 Summary802
- References802
- Part VI: Theoretical Underpinnings and Future Directions805
- Chapter 36. Theoretical Underpinnings807
- 36.1 General Computational Array Model807
- 36.2 Implications of the General Model809
- 36.3 Induced Architectural Models814
- 36.4 Modeling Architectural Space816
- 36.5 Implications826
- References828
- Chapter 37. Defect and Fault Tolerance829
- 37.1 Defects and Faults830
- 37.2 Defect Tolerance830
- 37.3 Transient Fault Tolerance843
- 37.4 Lifetime Defects848
- 37.5 Configuration Upsets849
- 37.6 Outlook850
- References851
- Chapter 38. Reconfigurable Computing and Nanoscale Architecture853
- 38.1 Trends in Lithographic Scaling854
- 38.2 Bottom-up Technology855
- 38.3 Challenges858
- 38.4 Nanowire Circuits859
- 38.5 Statistical Assembly862
- 38.6 Nanopla Architecture864
- 38.7 Nanoscale Design Alternatives870
- 38.8 Summary872
- References873
- Index877
Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap between the separate worlds of hardware and software design— the key feature of reconfigurable computing is its groundbreaking ability to perform computations in hardware to increase performance while retaining the flexibility of a software solution. Reconfigurable computers serve as affordable, fast, and accurate tools for developing designs ranging from single chip architectures to multi-chip and embedded systems.
Scott Hauck and Andre DeHon have assembled a group of the key experts in the fields of both hardware and software computing to provide an introduction to the entire range of issues relating to reconfigurable computing. FPGAs (field programmable gate arrays) act as the “computing vehicles to implement this powerful technology. Readers will be guided into adopting a completely new way of handling existing design concerns and be able to make use of the vast opportunities possible with reconfigurable logic in this rapidly evolving field.
• Designed for both hardware and software programmers
• Views of reconfigurable programming beyond standard programming languages
• Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways
Scott Hauck and Andre DeHon have assembled a group of the key experts in the fields of both hardware and software computing to provide an introduction to the entire range of issues relating to reconfigurable computing. FPGAs (field programmable gate arrays) act as the “computing vehicles to implement this powerful technology. Readers will be guided into adopting a completely new way of handling existing design concerns and be able to make use of the vast opportunities possible with reconfigurable logic in this rapidly evolving field.
• Designed for both hardware and software programmers
• Views of reconfigurable programming beyond standard programming languages
• Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways