See MIPS Run
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Table of contents
- Copyright Pageiv
- Contentsvii
- Forewordv
- Prefacexv
- Style and Limitsxviii
- Conventionsxviii
- Acknowledgmentsxix
- Chapter 1. RISCs and MIPS Architectures1
- 1.1 Pipelines2
- 1.2 The MIPS Five-Stage Pipeline5
- 1.3 RISC and CISC7
- 1.4 Great MIPS Chips of the Past and Present8
- 1.5 MIPS Compared with CISC Architectures23
- Chapter 2. MIPS Architecture29
- 2.1 A Flavor of MIPS Assembly Language33
- 2.2 Registers34
- 2.3 Integer Multiply Unit and Registers38
- 2.4 Loading and Storing: Addressing Modes39
- 2.5 Data Types in Memory and Registers39
- 2.6 Synthesized Instructions in Assembly Language42
- 2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions43
- 2.8 Basic Address Space47
- 2.9 Pipeline Visibility50
- Chapter 3. Coprocessor 0: MIPS Processor Control53
- 3.1 CPU Control Instructions55
- 3.2 Which Registers Are RelevantWhen?58
- 3.3 CPU Control Registers and Their Encoding59
- 3.4 CP0 Hazards„A Trap for the Unwary75
- Chapter 4. How CachesWork on MIPS Processors79
- 4.1 Caches and Cache Management79
- 4.2 How CachesWork80
- 4.3 Write-Through Caches in Early MIPS CPUs83
- 4.4 Write-Back Caches in MIPS CPUs83
- 4.5 Other Choices in Cache Design84
- 4.6 Managing Caches85
- 4.7 L2 and L3 Caches88
- 4.8 Cache Configurations for MIPS CPUs88
- 4.9 Programming MIPS32/64 Caches90
- 4.10 Cache Efficiency98
- 4.11 Reorganizing Software to Influence Cache Efficiency100
- 4.12 Cache Aliases102
- Chapter 5. Exceptions, Interrupts, and Initialization105
- 5.1 Precise Exceptions107
- 5.2 When Exceptions Happen109
- 5.3 Exception Vectors:Where Exception Handling Starts109
- 5.4 Exception Handling: Basics113
- 5.5 Returning from an Exception114
- 5.6 Nesting Exceptions114
- 5.7 An Exception Routine115
- 5.8 Interrupts115
- 5.9 Starting Up124
- 5.10 Emulating Instructions128
- Chapter 6. Low-level Memory Management and the TLB131
- 6.1 The TLB/MMU Hardware andWhat It Does131
- 6.2 TLB/MMU Registers Described132
- 6.3 TLB/MMU Control Instructions140
- 6.4 Programming the TLB141
- 6.5 Hardware-Friendly Page Tables and Refill Mechanism143
- 6.6 Everyday Use of the MIPS TLB147
- 6.7 Memory Management in a Simpler OS149
- Chapter 7. Floating-Point Support151
- 7.1 A Basic Description of Floating Point151
- 7.2 The IEEE 754 Standard and Its Background152
- 7.3 How IEEE Floating-Point Numbers Are Stored154
- 7.4 MIPS Implementation of IEEE 754158
- 7.5 Floating-Point Registers159
- 7.6 Floating-Point Exceptions/Interrupts161
- 7.7 Floating-Point Control: The Control/Status Register161
- 7.8 Floating-Point Implementation Register165
- 7.9 Guide to FP Instructions166
- 7.10 Paired-Single Floating-Point Instructions and the MIPS-3D ASE173
- 7.11 Instruction Timing Requirements179
- 7.12 Instruction Timing for Speed179
- 7.13 Initialization and Enabling on Demand180
- 7.14 Floating-Point Emulation181
- Chapter 8. Complete Guide to the MIPS Instruction Set183
- 8.1 A Simple Example183
- 8.2 Assembly Instructions andWhat They Mean185
- 8.3 Floating-Point Instructions210
- 8.4 Differences in MIPS32/64 Release 1216
- 8.5 Peculiar Instructions and Their Purposes218
- 8.6 Instruction Encodings233
- 8.7 Instructions by Functional Group252
- Chapter 9. Reading MIPS Assembly Language263
- 9.1 A Simple Example264
- 9.2 Syntax Overview268
- 9.3 General Rules for Instructions269
- 9.4 Addressing Modes271
- 9.5 Object File and Memory Layout274
- Chapter 10. Porting Software to the MIPS Architecture279
- 10.1 Low-Level Software for MIPS Applications: A Checklist of Frequently Encountered Problems280
- 10.2 Endianness: Words, Bytes, and Bit Order281
- 10.3 Trouble with Visible Caches296
- 10.4 Memory Access Ordering and Reordering301
- 10.5 Writing it in C305
- Chapter 11. MIPS Software Standards (ABIs)311
- 11.1 Data Representations and Alignment312
- 11.2 Argument Passing and Stack Conventions for MIPS ABIs319
- Chapter 12. Debugging MIPS Designs„Debug and Profiling Features339
- 12.1 The EJTAGŽ On-chip Debug Unit341
- 12.2 Pre-EJTAG Debug Support„Break Instruction and CP0 Watchpoints358
- 12.3 PDtrace359
- 12.4 Performance Counters360
- Chapter 13. GNU/Linux from Eight Miles High363
- 13.1 Components364
- 13.2 Layering in the Kernel368
- Chapter 14. How Hardware and Software Work Together371
- 14.1 The Life and Times of an Interrupt371
- 14.2 Threads, Critical Regions, and Atomicity375
- 14.3 What Happens on a System Call378
- 14.4 How Addresses Get Translated in Linux/MIPS Systems380
- Chapter 15. MIPS Specific Issues in the Linux Kernel399
- 15.1 Explicit Cache Management399
- 15.2 CP0 Pipeline Hazards403
- 15.3 Multiprocessor Systems and Coherent Caches403
- 15.4 Demon Tweaks for a Critical Routine406
- Chapter 16. Linux Application Code, PIC, and Libraries409
- 16.1 How Link Units Get into a Program411
- 16.2 Global Offset Table (GOT) Organization412
- Appendix A. MIPS Multithreading415
- A.1 What Is Multithreading?415
- A.2 Why Is MT Useful?417
- A.3 How to Do Multithreading for MIPS417
- A.4 MT in Action421
- Appendix B. Other Optional Extensions to the MIPS Instruction Set425
- B.1 MIPS16 and MIPS16e ASEs425
- B.2 The MIPS DSP ASE428
- B.3 The MDMX ASE429
- MIPS Glossary431
- References477
- Books and Articles477
- Online Resources478
- Index481
This second edition is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and then describes the MIPS instruction set and programmers’ resources. It uses the MIPS32 standard as a baseline (the 1st edition used the R3000) from which to compare all other versions of the architecture and assumes that MIPS64 is the main option. The second part is a significant change from the first edition. It provides concrete examples of operating system low level code, by using Linux as the example operating system. It describes how Linux is built on the foundations the MIPS hardware provides and summarizes the Linux application environment, describing the libraries, kernel device-drivers and CPU-specific code. It then digs deep into application code and library support, protection and memory management, interrupts in the Linux kernel and multiprocessor Linux.
Sweetman has revised his best-selling MIPS bible for MIPS programmers, embedded systems designers, developers and programmers, who need an in-depth understanding of the MIPS architecture and specific guidance for writing software for MIPS-based systems, which are increasingly Linux-based.
* Completely new material offers the best explanation available on how Linux runs on real hardware.
* Provides a complete, updated and easy-to-use guide to the MIPS instruction set using the MIPS32 standard as the baseline architecture with the MIPS64 as the main option.
* Retains the same engaging writing style that made the first edition so readable, reflecting the authors 20+ years experience in designing systems based on the MIPS architecture.
Sweetman has revised his best-selling MIPS bible for MIPS programmers, embedded systems designers, developers and programmers, who need an in-depth understanding of the MIPS architecture and specific guidance for writing software for MIPS-based systems, which are increasingly Linux-based.
* Completely new material offers the best explanation available on how Linux runs on real hardware.
* Provides a complete, updated and easy-to-use guide to the MIPS instruction set using the MIPS32 standard as the baseline architecture with the MIPS64 as the main option.
* Retains the same engaging writing style that made the first edition so readable, reflecting the authors 20+ years experience in designing systems based on the MIPS architecture.