Elsevier S & T

System-on-Chip Test Architectures: Nanometer Design for Testability

Wang, Laung-Terng; Stroud, Charles E.; Touba, Nur A.

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Table of contents

Title pageiii
Copyright Pageiv
Table of Contentsv
Prefacexxi
In the Classroomxxvii
Acknowledgmentsxxix
Contributorsxxxi
About the Editorsxxxv
Chapter 1 Introduction1
1.1 Importance of System-on-Chip Testing2
1.1.1 Yield and Reject Rate5
1.1.2 Reliability and System Availability6
1.2 Basics of SOC Testing8
1.2.1 Boundary Scan (IEEE 1149.1 Standard)9
1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard)11
1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687)13
1.2.4 Core-Based Testing (IEEE 1500 Standard)13
1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard)17
1.3 Basics of Memory Testing20
1.4 SOC Design Examples24
1.4.1 BioMEMS Sensor25
1.4.2 Network-on-Chip Processor27
1.5 About This Book30
1.5.1 DFT Architectures30
1.5.2 New Fault Models and Advanced Techniques31
1.5.3 Yield and Reliability Enhancement32
1.5.4 Nanotechnology Testing Aspects33
1.6 Exercises33
Acknowledgments36
References36
Chapter 2 Digital Test Architectures41
2.1 Introduction41
2.2 Scan Design43
2.2.1 Scan Architectures44
2.2.1.1 Muxed-D Scan Design44
2.2.1.2 Clocked-Scan Design46
2.2.1.3 LSSD Scan Design47
2.2.1.4 Enhanced-Scan Design48
2.2.2 Low-Power Scan Architectures50
2.2.2.1 Reduced-Voltage Low-Power Scan Design50
2.2.2.2 Reduced-Frequency Low-Power Scan Design50
2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design50
2.2.2.4 Bandwidth-Matching Low-Power Scan Design51
2.2.2.5 Hybrid Low-Power Scan Design52
2.2.3 At-Speed Scan Architectures52
2.3 Logic Built-In Self-Test57
2.3.1 Logic BIST Architectures58
2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS)58
2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO)59
2.3.2 Coverage-Driven Logic BIST Architectures61
2.3.2.1 Weighted Pattern Generation61
2.3.2.2 Test Point Insertion62
2.3.2.3 Mixed-Mode BIST64
2.3.2.4 Hybrid BIST65
2.3.3 Low-Power Logic BIST Architectures66
2.3.3.1 Low-Transition BIST Design66
2.3.3.2 Test-Vector-Inhibiting BIST Design67
2.3.3.3 Modified LFSR Low-Power BIST Design67
2.3.4 At-Speed Logic BIST Architectures68
2.3.4.1 Single-Capture68
2.3.4.2 Skewed-Load70
2.3.4.3 Double-Capture73
2.3.5 Industry Practices75
2.4 Test Compression76
2.4.1 Circuits for Test Stimulus Compression77
2.4.1.1 Linear-Decompression-Based Schemes77
2.4.1.2 Broadcast-Scan-Based Schemes81
2.4.1.3 Comparison85
2.4.2 Circuits for Test Response Compaction87
2.4.2.1 Space Compaction88
2.4.2.2 Time Compaction92
2.4.2.3 Mixed Time and Space Compaction93
2.4.3 Low-Power Test Compression Architectures94
2.4.4 Industry Practices95
2.5 Random-Access Scan Design97
2.5.1 Random-Access Scan Architectures98
2.5.1.1 Progressive Random-Access Scan Design100
2.5.1.2 Shift-Addressable Random-Access Scan Design101
2.5.2 Test Compression RAS Architectures103
2.5.3 At-Speed RAS Architectures105
2.6 Concluding Remarks106
2.7 Exercises106
Acknowledgments110
References111
Chapter 3 Fault-Tolerant Design123
3.1 Introduction123
3.2 Fundamentals of Fault Tolerance124
3.2.1 Reliability125
3.2.2 Mean Time to Failure (MTTF)126
3.2.3 Maintainability127
3.2.4 Availability127
3.3 Fundamentals of Coding Theory129
3.3.1 Linear Block Codes129
3.3.2 Unidirectional Codes135
3.3.2.1 Two-Rail Codes135
3.3.2.2 Berger Codes136
3.3.2.3 Constant Weight Codes136
3.3.3 Cyclic Codes137
3.4 Fault Tolerance Schemes142
3.4.1 Hardware Redundancy142
3.4.1.1 Static Redundancy142
3.4.1.2 Dynamic Redundancy146
3.4.1.3 Hybrid Redundancy148
3.4.2 Time Redundancy150
3.4.2.1 Repeated Execution150
3.4.2.2 Multiple Sampling of Outputs151
3.4.2.3 Diverse Recomputation152
3.4.3 Information Redundancy153
3.4.3.1 Error Detection153
3.4.3.2 Error Correction160
3.5 Industry Practices163
3.6 Concluding Remarks165
3.7 Exercises165
Acknowledgments168
References168
Chapter 4 System/Network-on-Chip Test Architectures171
4.1 Introduction172
4.2 System-on-Chip (SOC) Testing175
4.2.1 Modular Testing of SOCs175
4.2.2 Wrapper Design and Optimization177
4.2.3 TAM Design and Optimization179
4.2.4 Test Scheduling181
4.2.5 Modular Testing of Mixed-Signal SOCs185
4.2.6 Modular Testing of Hierarchical SOCs188
4.2.7 Wafer-Sort Optimization for Core-Based SOCs191
4.3 Network-on-Chip (NOC) Testing192
4.3.1 NOC Architectures192
4.3.2 Testing of Embedded Cores194
4.3.2.1 Reuse of On-Chip Network for Testing194
4.3.2.2 Test Scheduling196
4.3.2.3 Test Access Methods and Test Interface197
4.3.2.4 Efficient Reuse of Network198
4.3.2.5 Power-Aware and Thermal-Aware Testing202
4.3.3 Testing of On-Chip Networks203
4.3.3.1 Testing of Interconnect Infrastructures203
4.3.3.2 Testing of Routers205
4.3.3.3 Testing of Network Interfaces and Integrated System Testing208
4.4 Design and Test Practice: Case Studies209
4.4.1 SOC Testing for PNX8550 System Chip210
4.4.2 NOC Testing for a High-End TV System212
4.5 Concluding Remarks215
4.6 Exercises216
Acknowledgments217
References217
Chapter 5 SIP Test Architectures225
5.1 Introduction226
5.1.1 SIP Definition226
5.1.2 SIP Examples227
5.1.3 Yield and Quality Challenges230
5.1.4 Test Strategy233
5.2 Bare Die Test235
5.2.1 Mechanical Probing Techniques235
5.2.2 Electrical Probing Techniques237
5.2.3 Reliability Screens240
5.3 Functional System Test242
5.3.1 Path-Based Testing242
5.3.2 Loopback Techniques: DFT and DSP245
5.4 Test of Embedded Components246
5.4.1 SIP Test Access Port247
5.4.2 Interconnections250
5.4.3 Digital and Memory Dies251
5.4.4 Analog and RF Components253
5.4.4.1 Test Equipment Issues253
5.4.4.2 Test of Analog, Mixed-Signal, and RF Dies254
5.4.5 MEMS255
5.5 Concluding Remarks257
5.6 Exercises257
Acknowledgments258
References258
Chapter 6 Delay Testing263
6.1 Introduction263
6.2 Delay Test Application265
6.2.1 Enhanced Scan266
6.2.2 Muxed-D Scan266
6.2.3 Scan Clocking266
6.2.4 Faster-Than-At-Speed Testing268
6.3 Delary Fault Models269
6.3.1 Transition Fault Model269
6.3.2 Inline-Delay Fault Model270
6.3.3 Gate-Delay Fault Model270
6.3.4 Path-Delay Fault Model270
6.3.5 Defect-Based Delay Fault Models271
6.4 Delay Test Sensitization276
6.5 Delay Fault Simulation277
6.5.1 Transition Fault Simulation277
6.5.2 Gate/Line Delay Fault Simulation277
6.5.3 Path-Delay Fault Simulation278
6.5.4 Defect-Based Delay Fault Model Simulation278
6.6 Delay Fault Test Generation280
6.6.1 Transition/Inline Fault ATPG280
6.6.2 Gate-Delay Fault ATPG282
6.6.3 Path-Delay Fault ATPG282
6.6.4 K Longest Paths per Gate (KLPG) ATPG283
6.7 Pseudo-Functional Testing to Avoid Over-Testing288
6.7.1 Computing Constraints290
6.7.1.1 Pair-Wise Constraints291
6.7.1.2 Multiliteral Constraints291
6.7.2 Constrained ATPG293
6.8 Concluding Remarks294
6.9 Exercises295
Acknowledgments299
References300
Chapter 7 Low-Power Testing307
7.1 Introduction307
7.2 Energy and Power Modeling309
7.2.1 Basics of Circuit Theory310
7.2.2 Terminology311
7.2.3 Test-Power Modeling and Evaluation312
7.3 Test Power Issues313
7.3.1 Thermal Effects314
7.3.2 Noise Phenomena314
7.3.3 Miscellaneous Issues315
7.4 Low-Power Scan Testing316
7.4.1 Basics of Scan Testing316
7.4.2 ATPG and X-Filling Techniques318
7.4.3 Low-Power Test Vector Compaction320
7.4.4 Shift Control Techniques321
7.4.5 Scan Cell Ordering322
7.4.6 Scan Architecture Modification324
7.4.7 Scan Clock Splitting326
7.5 Low-Power Built-In Self-Test328
7.5.1 Basics of Logic BIST328
7.5.2 LFSR Tuning329
7.5.3 Low-Power Test Pattern Generators330
7.5.4 Vector Filtering BIST331
7.5.5 Circuit Partitioning332
7.5.6 Power-Aware Test Scheduling334
7.6 Low-Power Test Data Compression335
7.6.1 Coding-Based Schemes336
7.6.2 Linear-Decompression-Based Schemes336
7.6.3 Broadcast-Scan-Based Schemes337
7.7 Low-Power RAM Testing339
7.8 Concluding Remarks341
7.9 Exercises342
Acknowledgments344
References344
Chapter 8 Coping with Physical Failures, Soft Errors, and Reliability Issues351
8.1 Introduction352
8.2 Signal Integrity354
8.2.1 Basic Concept of Integrity Loss354
8.2.2 Sources of Integrity Loss356
8.2.2.1 Interconnects356
8.2.2.2 Power Supply Noise358
8.2.2.3 Process Variations358
8.2.3 Integrity Loss Sensors/Monitors360
8.2.3.1 Current Sensor360
8.2.3.2 Power Supply Noise Monitor361
8.2.3.3 Noise Detector (ND) Sensor362
8.2.3.4 Integrity Loss Sensor (ILS)362
8.2.3.5 Jitter Monitor363
8.2.3.6 Process Variation Sensor364
8.2.4 Readout Architectures365
8.2.4.1 BIST-Based Architecture365
8.2.4.2 Scan-Based Architecture367
8.2.4.3 PV-Test Architecture368
8.3 Manufacturing Defects, Process Variations, and Reliability370
8.3.1 Fault Detection370
8.3.1.1 Structural Tests371
8.3.1.2 Defect-Based Tests372
8.3.1.3 Functional Tests378
8.3.2 Reliability Stress379
8.3.3 Redundancy and Memory Repair381
8.3.4 Process Sensors and Adaptive Design382
8.3.4.1 Process Variation Sensor383
8.3.4.2 Thermal Sensor383
8.3.4.3 Dynamic Voltage Scaling385
8.4 Soft Errors386
8.4.1 Sources of Soft Errors and SER Trends387
8.4.2 Coping with Soft Errors390
8.4.2.1 Fault Tolerance390
8.4.2.2 Error-Resilient Microarchitectures394
8.4.2.3 Soft Error Mitigation398
8.5 Defect and Error Tolerance402
8.5.1 Defect Tolerance404
8.5.2 Error Tolerance405
8.6 Concluding Remarks407
8.7 Exercises407
Acknowledgments409
References409
Chapter 9 Design for Manufacturability and Yield423
9.1 Introduction423
9.2 Yield426
9.3 Components of Yield427
9.3.1 Yield Models428
9.3.2 Yield and Repair429
9.4 Photolithography430
9.5 DFM and DFY433
9.5.1 Photolithography435
9.5.2 Critical Area439
9.5.3 Yield Variation over Time441
9.5.4 DFT and DFM/DFY444
9.6 Variability445
9.6.1 Sources of Variability445
9.6.2 Deterministic versus Random Variability446
9.6.3 Variability versus Defectivity448
9.6.4 Putting It All Together449
9.7 Metrics for DFX449
9.7.1 The Ideal Case450
9.7.2 Potential DFY Metrics452
9.7.2.1 Critical Area452
9.7.2.2 RET-Based Metrics452
9.7.2.3 Example DRC-Based Metrics for DFM454
9.8 Concluding Remarks456
9.9 Exercises457
Acknowledgments458
References459
Chapter 10 Design for Debug and Diagnosis463
10.1 Introduction463
10.1.1 What Are Debug and Diagnosis?464
10.1.2 Where Is Diagnosis Used?465
10.1.3 IC-Level Debug and Diagnosis465
10.1.4 Silicon Debug versus Defect Diagnosis466
10.1.5 Design for Debug and Diagnosis467
10.2 Logic Design for Debug and Diagnosis (DFD) Structures468
10.2.1 Scan468
10.2.2 Observation-Only Scan469
10.2.3 Observation Points with Multiplexers471
10.2.4 Array Dump and Trace Logic Analyzer472
10.2.5 Clock Control473
10.2.6 Partitioning, Isolation, and De-featuring475
10.2.7 Reconfigurable Logic476
10.3 Probing Technologies476
10.3.1 Mechanical Probing477
10.3.2 Injection-Based Probing478
10.3.2.1 E-beam Probing478
10.3.2.2 Laser Voltage Probing479
10.3.3 Emission-Based Probing483
10.3.3.1 Infrared Emission Microscopy (IREM)483
10.3.3.2 Picosecond Imaging Circuit Analysis (PICA)485
10.3.3.3 Time Resolved Emissions (TRE)486
10.4 Circuit Editing487
10.4.1 Focused Ion Beam487
10.4.2 Layout-Database-Driven Navigation System488
10.4.3 Spare Gates and Spare Wires489
10.5 Physical DFD Structures490
10.5.1 Physical DFD for Pico-Probing490
10.5.2 Physical DFD for E-Beam491
10.5.3 Physical DFD for FIB and Probing492
10.6 Diagnosis and Debug Process492
10.6.1 Diagnosis Techniques and Strategies495
10.6.2 Silicon Debug Process and Flow496
10.6.3 Debug Techniques and Methodology497
10.7 Concluding Remarks498
10.8 Exercises499
Acknowledgments500
References500
Chapter 11 Software-Based Self-Testing505
11.1 Introduction506
11.2 Software-Based Self-Testing Paradigm507
11.2.1 Self-Test Flow508
11.2.2 Comparison with Structural BIST509
11.3 Processor Functional Fault Self-Testing510
11.3.1 Processor Model510
11.3.2 Functional-Level Fault Models512
11.3.3 Test Generation Procedures513
11.3.3.1 Test Generation for Register Decoding Fault513
11.3.3.2 Test Generation for Instruction Decoding and Control Fault514
11.3.3.3 Test Generation for Data Transfer and Storage Function515
11.3.3.4 Test Generation for Data Manipulation Function516
11.3.3.5 Test Generation Complexity516
11.4 Processor Structural Fault Self-Testing516
11.4.1 Test Flow516
11.4.1.1 Test Preparation516
11.4.1.2 Self-Testing517
11.4.2 Stuck-At Fault Testing518
11.4.2.1 Instruction-Imposed I/O Constraint Extraction518
11.4.2.2 Constrained Component Test Generation519
11.4.2.3 Test Program Synthesis521
11.4.2.4 Processor Self-Testing522
11.4.3 Test Program Synthesis Using Virtual Constraint Circuits (VCCs)523
11.4.4 Delay Fault Testing526
11.4.4.1 Functionally Untestable Delay Faults526
11.4.4.2 Constraint Extraction527
11.4.4.3 Test Program Generation528
11.4.5 Functional Random Instruction Testing529
11.5 Processor Self-Diagnosis530
11.5.1 Challenges to SBST-Based Processor Diagnosis530
11.5.2 Diagnostic Test Program Generation531
11.6 Testing Global Interconnect533
11.6.1 Maximum Aggressor (MA) Fault Model533
11.6.2 Processor-Based Address and Data Bus Testing534
11.6.2.1 Data Bus Testing534
11.6.2.2 Address Bus Testing535
11.6.3 Processor-Based Functional MA Testing536
11.7 Testing Nonprogrammable Cores536
11.7.1 Preprocessing Phase538
11.7.2 Core Test Phase538
11.8 Instruction-Level DFT538
11.8.1 Instruction-Level DFT Concept538
11.8.2 Testability Instructions539
11.8.3 Test Optimization Instructions541
11.9 DSP-Based Analog/Mixed-Signal Component Testing541
11.10 Concluding Remarks543
11.11 Exercises544
Acknowledgments545
References545
Chapter 12 Field Programmable Gate Array Testing549
12.1 Overview of FPGAs549
12.1.1 Architecture550
12.1.2 Configuration554
12.1.3 The Testing Problem556
12.2 Testing Approaches558
12.2.1 External Testing and Built-In Self-Test559
12.2.2 Online and Offline Testing560
12.2.3 Application Dependent and Independent Testing561
12.3 BIST of Programmable Resources562
12.3.1 Logic Resources563
12.3.1.1 Programmable Logic Blocks567
12.3.1.2 Input/Output Cells570
12.3.1.3 Specialized Cores571
12.3.1.4 Diagnosis575
12.3.2 Interconnect Resources578
12.4 Embedded Processor-Based Testing583
12.5 Concluding Remarks585
12.6 Exercises586
Acknowledgments587
References587
Chapter 13 MEMS Testing591
13.1 Introduction592
13.2 MEMS Testing Considerations593
13.3 Test Methods and Instrumentation for MEMS594
13.3.1 Electrical Test595
13.3.2 Optical Test Methods596
13.3.3 Material Property Measurements598
13.3.4 Failure Modes and Analysis599
13.3.5 Mechanical Test Methods600
13.3.6 Environmental Testing607
13.4 RF MEMS Devices609
13.4.1 RF MEMS Switches610
13.4.2 RF MEMS Resonators611
13.5 Optical MEMS Devices614
13.6 Fluidic MEMS Devices616
13.6.1 MEMS Pressure Sensor617
13.6.2 MEMS Humidity Sensor618
13.7 Dynamic MEMS Devices620
13.7.1 MEMS Microphone620
13.7.2 MEMS Accelerometer621
13.7.3 MEMS Gyroscope622
13.8 Testing Digital Microfluidic Biochips625
13.8.1 Overview of Digital Microfluidic Biochips626
13.8.2 Fault Modeling627
13.8.3 Test Techniques628
13.8.4 Application to a Fabricated Biochip631
13.9 DFT and BIST for MEMS633
13.9.1 Overview of DFT and BIST Techniques633
13.9.2 MEMS BIST Examples637
13.10 Concluding Remarks643
13.11 Exercises644
Acknowledgments646
References646
Chapter 14 High-Speed I/O Interfaces653
14.1 Introduction654
14.2 High-Speed I/O Architectures657
14.2.1 Global Clock I/O Architectures657
14.2.2 Source Synchronous I/O Architectures658
14.2.3 Embedded Clock I/O Architectures660
14.2.3.1 Jitter Components661
14.2.3.2 Jitter Separation662
14.2.3.3 Jitter, Noise, and Bit-Error-Rate Interactions666
14.3 Testing of I/O Interfaces668
14.3.1 Testing of Global Clock I/O669
14.3.2 Testing of Source Synchronous I/O669
14.3.3 Testing of Embedded Clock High-Speed Serial I/O671
14.3.3.1 Transmitter671
14.3.3.2 Channel or Medium673
14.3.3.3 Receiver675
14.3.3.4 Reference Clock677
14.3.3.5 System-Level Bit-Error-Rate Estimation678
14.3.3.6 Tester Apparatus Considerations678
14.4 DFT-Assisted Testing680
14.4.1 AC Loopback Testing681
14.4.2 High-Speed Serial-Link Loopback Testing683
14.4.3 Testing the Equalizers686
14.5 System-Level Interconnect Testing690
14.5.1 Interconnect Testing with Boundary Scan690
14.5.2 Interconnect Testing with High-Speed Boundary Scan691
14.5.3 Interconnect Built-In Self-Test693
14.6 Future Challenges694
14.7 Concluding Remarks695
14.8 Exercises696
Acknowledgments697
References697
Chapter 15 Analog and Mixed-Signal Test Architectures703
15.1 Introduction704
15.2 Analog Functional Testing705
15.2.1 Frequency Response Testing705
15.2.2 Linearity Testing707
15.2.3 Signal-to-Noise Ratio Testing709
15.2.4 Quantization Noise710
15.2.5 Phase Noise712
15.2.6 Noise in Phase-Locked Loops715
15.2.6.1 In-Band PLL Phase Noise716
15.2.6.2 Out-Band PLL Phase Noise718
15.2.6.3 Optimal Loop Setting718
15.2.7 DAC Nonlinearity Testing719
15.3 Analog and Mixed-Signal Test Architectures720
15.4 Defect-Oriented Mixed-Signal BIST Approaches724
15.5 FFT-Based Mixed-Signal BIST727
15.5.1 FFT727
15.5.2 Inverse FFT729
15.5.3 FFT-Based BIST Architecture729
15.5.4 FFT-Based Output Response Analysis730
15.5.5 FFT-Based Test Pattern Generation731
15.6 Direct Digital Synthesis BIST733
15.6.1 DDS-Based BIST Architecture734
15.6.2 Frequency Response Test and Measurement736
15.6.3 Linearity Test and Measurement738
15.6.4 SNR and Noise Figure Measurement739
15.7 Concluding Remarks739
15.8 Exercises740
Acknowledgments741
References741
Chapter 16 RF Testing745
16.1 Introduction746
16.1.1 RF Basics746
16.1.2 RF Applications748
16.2 Key Specifications for RF Systems750
16.2.1 Test Instrumentation750
16.2.1.1 Spectrum Analyzer751
16.2.1.2 Network Analyzer752
16.2.1.3 Noise Figure Meter753
16.2.1.4 Phase Meter755
16.2.2 Test Flow in Industry755
16.2.2.1 Design and Fabrication756
16.2.2.2 Characterization Test756
16.2.2.3 Production Test756
16.2.3 Characterization Test and Production Test757
16.2.3.1 Accuracy757
16.2.3.2 Time Required for Testing758
16.2.3.3 Cost of Testing758
16.2.4 Circuit-Level Specifications758
16.2.4.1 Gain759
16.2.4.2 Harmonics and Third-Order Intercept Point (IP3)759
16.2.4.3 1-dB Compression Point (P–1dB)763
16.2.4.4 Total Harmonic Distortion (THD)763
16.2.4.5 Gain Flatness764
16.2.4.6 Noise Figure765
16.2.4.7 Sensitivity and Dynamic Range767
16.2.4.8 Local Oscillator Leakage768
16.2.4.9 Phase Noise768
16.2.4.10 Adjacent Channel Power Ratio769
16.2.5 System-Level Specifications770
16.2.5.1 I-Q Mismatch770
16.2.5.2 Error Vector Magnitude771
16.2.5.3 Modulation Error Ratio772
16.2.5.4 Bit Error Rate773
16.2.6 Structure of RF Systems774
16.3 Test Hardware: Tester and DIB/PIB776
16.4 Repeatability and Accuracy779
16.5 Industry Practices for High-Volume Manufacturing782
16.5.1 Test Cost Analysis783
16.5.2 Key Trends784
16.6 Concluding Remarks785
16.7 Exercises786
Acknowledgments787
References788
Chapter 17 Testing Aspects of Nanotechnology Trends791
17.1 Introduction792
17.2 Resonant Tunneling Diodes and Quantum-Dot Cellular Automata794
17.2.1 Testing Threshold Networks with Application to RTDs795
17.2.2 Testing Majority Networks with Application to QCA799
17.3 Crossbar Array Architectures807
17.3.1 Hybrid Nanoscale/CMOS Structures810
17.3.1.1 The nanoPLA810
17.3.1.2 Molecular CMOS (CMOL)813
17.3.2 Built-In Self-Test815
17.3.3 Simultaneous Configuration and Test817
17.4 Carbon Nanotube (CNT) Field Effect Transistors820
17.4.1 Imperfection-Immune Circuits for Misaligned CNTs820
17.4.2 Robust Circuits for Metallic CNTs824
17.5 Concluding Remarks826
Acknowledgments826
References827
Index833

Book details

Vendor Elsevier S & T
SKU 9780123739735R150
ISBN-13 9780080556802
Author Wang, Laung-Terng; Stroud, Charles E.; Touba, Nur A.
Category Computers
Subject Logic Design

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Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost.

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

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