Elsevier S & T

VHDL Coding and Logic Synthesis with Synopsys

Lee, Weng Fook

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Table of contents
  • Cover
  • Table of Contentsvii
  • List of Figuresxi
  • List of Tablesxv
  • List of Examplesxvii
  • Prefacexix
  • Acknowledgmentxxiii
  • Trademarksxxiv
  • Part I: VHDL CODING1
  • Chapter 1. Introduction3
  • 1.1 Conventional Design„Schematic Capture3
  • 1.2 Hardware Description Language4
  • 1.3 VHDL Design Structure4
  • 1.4 Component Instantiation Within a VHDL Design Structure8
  • 1.5 Structural, Behavioral, and Synthesizable VHDL Design Structure10
  • 1.6 Usage of Library Declarations in VHDL Design Structure17
  • Chapter 2. VHDL Simulation and Synthesis Flow19
  • Chapter 3. Synthesizable Code for Basic Logic Components21
  • 3.1 AND Logic21
  • 3.2 OR Logic22
  • 3.3 NOT Logic24
  • 3.4 NAND Logic24
  • 3.5 NOR Logic26
  • 3.6 Tristate Buffer Logic27
  • 3.7 Complex Logic Gate28
  • 3.8 Latch29
  • 3.9 Flip-Flop33
  • 3.10 Decoder34
  • 3.11 Encoder36
  • 3.12 Multiplexer38
  • 3.13 Priority Encoder39
  • 3.14 Memory Cell42
  • 3.15 Adder43
  • 3.16 Component Inference45
  • Chapter 4. SignaI Versus Variable47
  • 4.1 Variable47
  • 4.2 Signal48
  • 4.3 When to Use Signal and When to Use Variable52
  • 4.4 Usage of Loopback Signal53
  • Chapter 5. Examples of Complex Synthesizable Code57
  • 5.1 Shifter57
  • 5.2 Counter67
  • 5.3 Memory Module73
  • 5.4 Car Traffic Controller81
  • Chapter 6. Pipeline Microcontroller Synthesizable Design87
  • 6.1 Instruction Set Definition87
  • 6.2 Architectural Definition88
  • 6.3 Pipeline Definition91
  • 6.4 Microarchitecture Definition for the Pipeline Microcontroller92
  • Part II: LOGIC SYNTHESIS WITH SYNOPSYS145
  • Chapter 7. Timing Considerations in Design147
  • 7.1 Setup Timing Violation147
  • 7.2 Hold Timing Violation148
  • 7.3 Setup/Hold Timing Considerations in Synthesis149
  • 7.4 Microarchitectural Tweaks for Fixing Setup Time Violations150
  • 7.5 Microarchitectural Tweaks for Fixing Hold Time Violations154
  • 7.6 Asynchronous/False Paths155
  • 7.7 Multicycle Paths155
  • Chapter 8. VHDL Synthesis with Timing Constraints157
  • 8.1 Introduction to Design Compiler157
  • 8.2 Using Design Compiler for Synthesis158
  • 8.3 Performance Tweaks161
  • 8.4 Area Optimization in Synthesis Tweaks192
  • 8.5 Fixing Hold-Time Violations in Synopsys195
  • 8.6 Misc Synthesis Commands Generally Used195
  • 8.7 Top-Down and Bottoms-Up Compilation225
  • Chapter 9. GTECH Instantiation229
  • Chapter 10. DesignWare Library231
  • 10.1 Creating Your Own DesignWare Library235
  • Chapter 11. Testability Issues in Synthesis243
  • 11.1 Multiplexed Flip-Flop Scan Style244
  • 11.2 Using Synopsys Test Compiler for Scan Insertion246
  • Chapter 12. FPGA Synthesis253
  • Chapter 13. Synthesis Links to Layout263
  • 13.1 Forward-Annotation263
  • 13.2 Wireload Models264
  • 13.3 Floorplanning a Design266
  • 13.4 Post Layout Optimization267
  • Chapter 14. Design Guideline to Follow for Efficient Synthesis269
  • Appendix A. (STD_LOGIC_1164 Library)271
  • Appendix B. (Shifter Synthesis Results)303
  • Appendix C. (Counter Synthesis Results)309
  • Appendix D. (Pipeline Microcontroller Synthesis Results„Top-Down Compilation)313
  • Appendix E. (EDIF File of Synthesized Microcontroller Example from Chapter 6)329
  • Appendix F. (SDF File from Synthesized Microcontroller Example of Chapter 6)355
  • Glossary385
  • Bibliography387
  • Index389
Book details
  • Vendor Elsevier S & T
  • SKU 9780124406513
  • ISBN-13 9780080520506
  • Author Lee, Weng Fook
  • Category Technology & Engineering
  • Subject Digital

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This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas.

Synopsys is the dominant computer-aided circuit design program in the world. All of the major circuit manufacturers and ASIC design firms use Synopsys. In addition, Synopsys is used in teaching and laboratories at over 600 universities.


* First practical guide to using synthesis with Synopsys
* Synopsys is the #1 design program for IC design