Elsevier S & T

Virtual Machines: Versatile Platforms for Systems and Processes

Smith, Jim; Nair, Ravi

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Table of contents
  • Virtual Machines: Versatile Platforms for Systems and ProcessesCover
  • Cover
  • Cover
  • Contentsxix
  • Contentsxix
  • Forewordix
  • Forewordix
  • Prefacexi
  • Prefacexi
  • Chapter One. Introduction to Virtual Machines1
  • Chapter One. Introduction to Virtual Machines1
  • 1.1 Computer Architecture6
  • 1.1 Computer Architecture6
  • 1.2 Virtual Machine Basics9
  • 1.2 Virtual Machine Basics9
  • 1.3 Process Virtual Machines13
  • 1.3 Process Virtual Machines13
  • 1.4 System Virtual Machines17
  • 1.4 System Virtual Machines17
  • 1.5 A Taxonomy22
  • 1.5 A Taxonomy22
  • 1.6 Summary: The Versatility of Virtual Machines23
  • 1.6 Summary: The Versatility of Virtual Machines23
  • 1.7 The Rest of the Book24
  • 1.7 The Rest of the Book24
  • Chapter Two. Emulation: Interpretation and Binary Translation27
  • Chapter Two. Emulation: Interpretation and Binary Translation27
  • 2.1 Basic Interpretation29
  • 2.1 Basic Interpretation29
  • 2.2 Threaded Interpretation32
  • 2.2 Threaded Interpretation32
  • 2.3 Predecoding and Direct Threaded Interpretation34
  • 2.3 Predecoding and Direct Threaded Interpretation34
  • 2.4 Interpreting a Complex Instruction Set38
  • 2.4 Interpreting a Complex Instruction Set38
  • 2.5 Binary Translation49
  • 2.5 Binary Translation49
  • 2.6 Code Discovery and Dynamic Translation52
  • 2.6 Code Discovery and Dynamic Translation52
  • 2.7 Control Transfer Optimizations64
  • 2.7 Control Transfer Optimizations64
  • 2.8 Instruction Set Issues68
  • 2.8 Instruction Set Issues68
  • 2.9 Case Study: Shade and the Role of Emulation During Simulation77
  • 2.9 Case Study: Shade and the Role of Emulation During Simulation77
  • 2.10 Summary: Performance Tradeoffs80
  • 2.10 Summary: Performance Tradeoffs80
  • Chapter Three. Process Virtual Machines83
  • Chapter Three. Process Virtual Machines83
  • 3.1 Virtual Machine Implementation85
  • 3.1 Virtual Machine Implementation85
  • 3.2 Compatibility87
  • 3.2 Compatibility87
  • 3.3 State Mapping95
  • 3.3 State Mapping95
  • 3.4 Memory Architecture Emulation102
  • 3.4 Memory Architecture Emulation102
  • 3.5 Instruction Emulation114
  • 3.5 Instruction Emulation114
  • 3.6 Exception Emulation119
  • 3.6 Exception Emulation119
  • 3.7 Operating System Emulation128
  • 3.7 Operating System Emulation128
  • 3.8 Code Cache Management133
  • 3.8 Code Cache Management133
  • 3.9 System Environment140
  • 3.9 System Environment140
  • 3.10 Case Study: FX!32142
  • 3.10 Case Study: FX!32142
  • 3.11 Summary145
  • 3.11 Summary145
  • Chapter Four. Dynamic Binary Optimization147
  • Chapter Four. Dynamic Binary Optimization147
  • 4.1 Dynamic Program Behavior153
  • 4.1 Dynamic Program Behavior153
  • 4.2 Profiling156
  • 4.2 Profiling156
  • 4.3 Optimizing Translation Blocks167
  • 4.3 Optimizing Translation Blocks167
  • 4.4 Optimization Framework180
  • 4.4 Optimization Framework180
  • 4.5 Code Reordering186
  • 4.5 Code Reordering186
  • 4.6 Code Optimizations201
  • 4.6 Code Optimizations201
  • 4.7 Same-ISA Optimization Systems: Special-Case Process Virtual Machines208
  • 4.7 Same-ISA Optimization Systems: Special-Case Process Virtual Machines208
  • 4.8 Summary218
  • 4.8 Summary218
  • Chapter Five. High-Level Language Virtual Machine Architecture221
  • Chapter Five. High-Level Language Virtual Machine Architecture221
  • 5.1 The Pascal P-Code Virtual Machine225
  • 5.1 The Pascal P-Code Virtual Machine225
  • 5.2 Object-Oriented High-Level Language Virtual Machines228
  • 5.2 Object-Oriented High-Level Language Virtual Machines228
  • 5.3 The Java Virtual Machine Architecture241
  • 5.3 The Java Virtual Machine Architecture241
  • 5.4 Completing the Platform: APIs261
  • 5.4 Completing the Platform: APIs261
  • 5.5 The Microsoft Common Language Infrastructure: A Flexible High-Level Language Virtual Machine267
  • 5.5 The Microsoft Common Language Infrastructure: A Flexible High-Level Language Virtual Machine267
  • 5.6 Summary: Virtual ISA Features275
  • 5.6 Summary: Virtual ISA Features275
  • Chapter Six. High-Level Language Virtual Machine Implementation281
  • Chapter Six. High-Level Language Virtual Machine Implementation281
  • 6.1 Dynamic Class Loading284
  • 6.1 Dynamic Class Loading284
  • 6.2 Implementing Security286
  • 6.2 Implementing Security286
  • 6.3 Garbage Collection294
  • 6.3 Garbage Collection294
  • 6.4 Java Native Interface304
  • 6.4 Java Native Interface304
  • 6.5 Basic Emulation305
  • 6.5 Basic Emulation305
  • 6.6 High-Performance Emulation306
  • 6.6 High-Performance Emulation306
  • 6.7 Case Study: The Jikes Research Virtual Machine320
  • 6.7 Case Study: The Jikes Research Virtual Machine320
  • 6.8 Summary327
  • 6.8 Summary327
  • Chapter Seven. Codesigned Virtual Machines329
  • Chapter Seven. Codesigned Virtual Machines329
  • 7.1 Memory and Register State Mapping333
  • 7.1 Memory and Register State Mapping333
  • 7.2 Self-Modifying and Self-Referencing Code337
  • 7.2 Self-Modifying and Self-Referencing Code337
  • 7.3 Support for Code Caching339
  • 7.3 Support for Code Caching339
  • 7.4 Implementing Precise Traps344
  • 7.4 Implementing Precise Traps344
  • 7.5 Input/Output351
  • 7.5 Input/Output351
  • 7.6 Applying Codesigned Virtual Machines352
  • 7.6 Applying Codesigned Virtual Machines352
  • 7.7 Case Study: Transmeta Crusoe354
  • 7.7 Case Study: Transmeta Crusoe354
  • 7.8 Case Study: IBM AS/400357
  • 7.8 Case Study: IBM AS/400357
  • 7.9 Summary367
  • 7.9 Summary367
  • Chapter Eight. System Virtual Machines369
  • Chapter Eight. System Virtual Machines369
  • 8.1 Key Concepts373
  • 8.1 Key Concepts373
  • 8.2 Resource Virtualization„Processors382
  • 8.2 Resource Virtualization„Processors382
  • 8.3 Resource Virtualization„Memory396
  • 8.3 Resource Virtualization„Memory396
  • 8.4 Resource Virtualization„Input/Output404
  • 8.4 Resource Virtualization„Input/Output404
  • 8.5 Performance Enhancement of System Virtual Machines415
  • 8.5 Performance Enhancement of System Virtual Machines415
  • 8.6 Case Study: VMware Virtual Platform426
  • 8.6 Case Study: VMware Virtual Platform426
  • 8.7 Case Study: The Intel VT-x (Vanderpool) Technology436
  • 8.7 Case Study: The Intel VT-x (Vanderpool) Technology436
  • 8.8 Summary442
  • 8.8 Summary442
  • Chapter Nine. Multiprocessor Virtualization445
  • Chapter Nine. Multiprocessor Virtualization445
  • 9.1 Partitioning of Multiprocessor Systems445
  • 9.1 Partitioning of Multiprocessor Systems445
  • 9.2 Physical Partitioning455
  • 9.2 Physical Partitioning455
  • 9.3 Logical Partitioning458
  • 9.3 Logical Partitioning458
  • 9.4 Case Study: Cellular Disco System Virtual Machine-Based Partitioning475
  • 9.4 Case Study: Cellular Disco System Virtual Machine-Based Partitioning475
  • 9.5 Virtualization with Different Host and Guest ISAs485
  • 9.5 Virtualization with Different Host and Guest ISAs485
  • 9.6 Summary496
  • 9.6 Summary496
  • Chapter Ten. Emerging Applications499
  • Chapter Ten. Emerging Applications499
  • 10.1 Security501
  • 10.1 Security501
  • 10.2 Migration of Computing Environments520
  • 10.2 Migration of Computing Environments520
  • 10.3 Grids: Virtual Organizations535
  • 10.3 Grids: Virtual Organizations535
  • 10.4 Summary552
  • 10.4 Summary552
  • Appendix A: Real Machines553
  • Appendix A: Real Machines553
  • A.1 Computer System Hardware554
  • A.1 Computer System Hardware554
  • A.2 The User ISA: Computation561
  • A.2 The User ISA: Computation561
  • A.3 The System ISA: Resource Management566
  • A.3 The System ISA: Resource Management566
  • A.4 Operating System Organization580
  • A.4 Operating System Organization580
  • A.5 The Operating System Interface583
  • A.5 The Operating System Interface583
  • A.6 System Initialization586
  • A.6 System Initialization586
  • A.7 Multiprocessor Architecture588
  • A.7 Multiprocessor Architecture588
  • A.8 Example Instruction Set Architectures600
  • A.8 Example Instruction Set Architectures600
  • References613
  • References613
  • Index629
  • Index629
Book details
  • Vendor Elsevier S & T
  • SKU 9781558609105R90
  • ISBN-13 9780080525402
  • Author Smith, Jim; Nair, Ravi
  • Category Computers
  • Subject General

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Virtual Machine technology applies the concept of virtualization to an entire machine, circumventing real machine compatibility constraints and hardware resource constraints to enable a higher degree of software portability and flexibility. Virtual machines are rapidly becoming an essential element in computer system design. They provide system security, flexibility, cross-platform compatibility, reliability, and resource efficiency. Designed to solve problems in combining and using major computer system components, virtual machine technologies play a key role in many disciplines, including operating systems, programming languages, and computer architecture. For example, at the process level, virtualizing technologies support dynamic program translation and platform-independent network computing. At the system level, they support multiple operating system environments on the same hardware platform and in servers.

Historically, individual virtual machine techniques have been developed within the specific disciplines that employ them (in some cases they aren’t even referred to as “virtual machines”), making it difficult to see their common underlying relationships in a cohesive way. In this text, Smith and Nair take a new approach by examining virtual machines as a unified discipline. Pulling together cross-cutting technologies allows virtual machine implementations to be studied and engineered in a well-structured manner. Topics include instruction set emulation, dynamic program translation and optimization, high level virtual machines (including Java and CLI), and system virtual machines for both single-user systems and servers.

* Examines virtual machine technologies across the disciplines that use them—operating systems, programming languages and computer architecture—defining a new and unified discipline.
* Reviewed by principle researchers at Microsoft, HP, and by other industry research groups.
* Written by two authors who combine several decades of expertise in computer system research and development, both in academia and industry.